PowerPC Microprocessor Family: The Programmer's Reference

MPRPPCPRG-01 MPCPRG/D

10/95

PowerPC



Microprocessor Family:

The Programmer’s Reference Guide



Motorola Inc. 1995

Portions hereof



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PowerPC Microprocessor Family: The Programmer’s Reference Guide

Introduction

The primary objective of this document is to provide a concise method by which system

software and hardware developers and application programmers may more readily provide

software that is compatible across the family of PowerPC processors and other devices. A

more detailed account of the following topics or the PowerPC architecture in general, may

be obtained from the

PowerPC Microprocessor Family: The Programming Environments

referred to as

The Programming Environments Manual

. (

The PowerPC Architecture: A

Speciﬁcation for a New Family of RISC Processors

deﬁnes the architecture from the

perspective of the three programming environments and remains the deﬁning document for

the PowerPC architecture.)

This document is divided into four parts:

• Part 1, “Register Summary,” on page 4 provides a brief overview of the PowerPC

and 64-bit registers.

• Part 2, “Memory Control Model,” on page 28 provides a brief outline of the page

table entry and segment table entry for both 32- and 64-bit implementations.

• Part 3, “Exception Vectors,” on page 40 provides a quick reference for exception

types and the conditions that cause them.

• Part 4, “PowerPC Instruction Set,” on page 41 provides detailed information on the

instruction ﬁeld summary—including syntax and notation conventions. Also

included, is the entire PowerPC instruction set, sorted by mnemonic and opcode.

In this document, the term “60x” is used to denote a 32-bit microprocessor from the

PowerPC architecture family. 60x processors implement the PowerPC architecture as it is

speciﬁed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer

data types of 8, 16, and 32 bits, and ﬂoating-point data types of 32 and 64 bits (single-

precision and double-precision).

Table 1 contains acronyms and abbreviations that are used in this document. Note that the

meanings for some acronyms (such as SDR1 and XER) are historical, and the words for

which an acronym stands may not be intuitively obvious.

This document was created with FrameMaker 4.0.4

PowerPC Microprocessor Family: The Programmer’s Reference Guide

Table 1. Acronyms and Abbreviated Terms

Term Meaning

ASR Address space register

BAT Block address translation

BUID Bus unit ID

CR Condition register

CTR Count register

DAR Data address register

DBAT Data BAT

DEC Decrementer register

DSISR Register used for determining the source of a DSI exception

DTLB Data translation lookaside buffer

EA Effective address

EAR External access register

FPR Floating-point register

FPSCR Floating-point status and control register

GPR General-purpose register

IBAT Instruction BAT

IEEE Institute of Electrical and Electronics Engineers

IU Integer unit

LR Link register

MMU Memory management unit

msb Most signiﬁcant bit

MSR Machine state register

NaN Not a number

No-Op No operation

OEA Operating environment architecture

PTE Page table entry

PTEG Page table entry group

PVR Processor version register

RISC Reduced instruction set computing

SDR1 Register that speciﬁes the page table base address for virtual-to-physical address translation

SIMM Signed immediate value

SLB Segment lookaside buffer

PowerPC Microprocessor Family: The Programmer’s Reference Guide

Table 2 describes instruction ﬁeld notation conventions used in this document.

SPR Special-purpose register

SPRG

Registers available for general purposes

SR Segment register

SRR0 Machine status save/restore register 0

SRR1 Machine status save/restore register 1

TB Time base register

TLB Translation lookaside buffer

UIMM Unsigned immediate value

UISA User instruction set architecture

VEA Virtual environment architecture

XER Register used for indicating conditions such as carries and overﬂows for integer operations

Table 2. Instruction Field Conventions

The Architecture Speciﬁcation Equivalent to:

BA, BB, BT

crb

D (respectively)

BF, BFA

crf

S (respectively)

DS ds

FLM FM

FRA, FRB, FRC, FRT, FRS

S (respectively)

FXM CRM

RA, RB, RT, RS

S (respectively)

SI SIMM

U IMM

UI UIMM

/, //, /// 0...0 (shaded)

Table 1. Acronyms and Abbreviated Terms (Continued)

Term Meaning

PowerPC Microprocessor Family: The Programmer’s Reference Guide

Part 1 Register Summary

This section describes the register organization deﬁned by the three levels of the PowerPC

architecture—user instruction set architecture (UISA), virtual environment architecture

(VEA), and operating environment architecture (OEA). The PowerPC architecture deﬁnes

instructions are accessed from the on-chip registers or are provided as immediate values

embedded in the opcode. The three-register instruction format allows speciﬁcation of a

target register distinct from the two source registers, thus preserving the original data for

use by other instructions and reducing the number of instructions required for certain

operations. Data is transferred between memory and registers with explicit load and store

instructions only.

Figure 1 shows a graphic representation of the entire PowerPC register set. The number to

the right of the register name indicates the number that is used in the syntax of the

instruction operands to access the register (for example, the number used to access the XER

is SPR1).

Many of the SPRs can be accessed only by supervisor-level instructions; any attempt to

access these SPRs with user-level instructions results in a supervisor-level exception. Some

SPRs are implementation-speciﬁc. In some cases, not all of a register’s bits are

implemented in hardware. When a PowerPC microprocessor detects SPR encodings other

than those deﬁned in this document, it either takes a program exception (if bit 0 of the SPR

encoding is set) or it treats the instruction as a no-op (if bit 0 of the SPR encoding is clear).

Note that the general purpose registers (GPRs), link register (LR), count register (CTR),

machine state register (MSR), data address register (DAR), SDR1, save and restore

registers 0 and 1 (SRR0 and SRR1), SPRG0–SPRG3, and data address breakpoint register

(DABR) are 64 bits in length in 64-bit implementations and 32 bits in length in 32-bit

implementations.

PowerPC Microprocessor Family: The Programmer’s Reference Guide

Figure 1. PowerPC Programming Model—Registers

FPR0

FPR1

FPR31

TBR 268

Time Base Facility

(Read-Only)

TBL

TBR 269

TBU

SUPERVISOR MODEL

Machine State Register

MSR

Processor Version Register

SPR 287PVR

Segment Registers

SR0

SR1

SR15

DSISR Register

SPR 18DSISR

Data Address Register

SPR 19DAR

Save and Restore Registers

SPR 26SRR0

SPR 27SRR1

SPRG Registers

SPR 272SPRG0

SPR 273SPRG1

SPR 274SPRG2

SPR 275SPRG3

SPR 22

Decrementer

DEC

Time Base Facility

(Write-Only)

SPR 284TBL

SPR 285TBU

SPR 282

External Address Register

EAR

SDR1 Register

SPR 25SDR1

Address Space Register

SPR 280ASR

Instruction BAT Registers

SPR 528IBAT0U

SPR 529IBAT0L

SPR 530IBAT1U

SPR 531IBAT1L

SPR 532IBAT2U

SPR 533IBAT2L

SPR 534IBAT3U

SPR 535IBAT3L

Data BAT Registers

SPR 536DBAT0U

SPR 537DBAT0L

SPR 538DBAT1U

SPR 539DBAT1L

SPR 540DBAT2U

SPR 541DBAT2L

SPR 542DBAT3U

SPR 543DBAT3L

Configuration Registers

Memory Management Registers

Exception Handling Registers

Miscellaneous Registers

SPR 1013DABR

Data Address

Breakpoint Register

These registers are in 32-bit implementations only.

These registers are in 64-bit implementations only.

These registers are optional in the PowerPC architecture.

SPR 1

USER MODEL

Floating-Point Status

and Control Register

FPSCR

Condition Register

GPR0

GPR1

GPR31

General-Purpose Registers

Floating-Point Registers

XER

SPR 8

Link Register

SPR 9

Count Register

CTR

XER Register

PowerPC Microprocessor Family: The Programmer’s Reference Guide

Table 3 provides a quick method by which to reference the SPR and TBR numbers and bit

ﬁelds for all 32-bit PowerPC registers. Note that reserved bits are shaded.

Table 3. Quick Reference Guide—32-Bit Registers

012345678910111213141516171819202122232425262728293031

Notes:

1. For all SPR numbers refer to Figure 1

2. Write-Only

3. Read-Only

012345678910111213141516

TBR 269

TBR 268

SPR 1013

SPR 529

SPR 528

SPR 287

SPR 285

SPR 284

SPR 282

SPR 272

SPR 27

SPR 26

SPR 25

Number

GPR

Name

MSR

CTR

DAR

SDR1

SRR0

SRR1

SPRG

PVR

BAT

DABR

TB(L)

TBU

Name

0 0 0 0 0 0 0 0 0 0 0 0 0

POW

SPR 22

SPR 19

SPR 18

SPR 9

SPR 8

SPR 1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

TB(L)

TBU

EAR

DEC

DSISR

XER

[T=1]

[T=0]

FPSCR

GPR

CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7

(For the FPSCR bits, refer to 1.4, “Floating-Point Status and Control Register (FPSCR),” on page 9.)

ILE PREE FP ME

FE0 FE1

BESE

IP IR DR

0 0

RI LE

VSID

0 0 0 0

TKs

BUID Controller-Speciﬁc Information

SO OV

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Byte Count

Branch Address

CTR

DSISR

DAR

DEC

HTABORG

0 0 0 0 0 0 0

HTABMASK

SRR0

0 0

SRR1

SPRG

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RID

TB(L)

TBU

TB(L)

TBU

Version Revision

BEPI

0 0 0 0

Vs Vp

BRPN

0 0 0 0 0 0 0 0 0 0

WIMG

DAB

PowerPC Microprocessor Family: The Programmer’s Reference Guide

Number

0 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263

Table 4 provides a quick method by which to reference the SPR and TBR numbers and bit

ﬁelds for all 64-bit PowerPC registers. Note that reserved bits are shaded.

1.1 General-Purpose Registers (GPRs)

Integer data is manipulated in the processor’s 32 GPRs shown in Figure 2. These registers

are 64-bit registers in 64-bit implementations and 32-bit registers in 32-bit

implementations. The GPRs are accessed as source and destination registers in the

instruction syntax.

Figure 2. General-Purpose Registers (GPRs)

1.2 Floating-Point Registers (FPRs)

The PowerPC architecture provides thirty-two 64-bit FPRs as shown in Figure 3. These

registers are accessed as source and destination registers for ﬂoating-point instructions.

Each FPR supports the double-precision ﬂoating-point format. Every instruction that

interprets the contents of an FPR as a ﬂoating-point value uses the double-precision

ﬂoating-point format for this interpretation.

Table 4. Quick Reference Guide—64-Bit Registers

GPR0

GPR1

. . .

GPR31

0 63/31

TBR 269

TBR 268

SPR 1013

SPR 529

SPR 528

SPR 280

SPR 272

SPR 27

SPR 26

SPR 25

SPR 19

SPR 9

SPR 8

Number

GPR

Name

FPR

MSR

CTR

DAR

SDR1

SRR0

SRR1

SPRG

ASR

BAT

DABR

TB(L)

TBU

Name

FPR

Branch Address

CTR

HTABORG

DAR

SRR0

SRR1

SPRG

BEPI

DAB

TB(L)

WIMG

TBU

0 0 0 0 0 0 0 0 0 0 0 0 0

HTABSIZE

0 0

Physical Address of Segment Table

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0

VsVp

BRPN

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Notes:

1. For all SPR numbers refer to Figure 1

2. Read-only

For the MSR bits, refer to 1.8, “Machine State Register (MSR),” on page 16.)

0 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263

PowerPC Microprocessor Family: The Programmer’s Reference Guide

All ﬂoating-point arithmetic instructions operate on data located in FPRs and, with the

exception of compare instructions, place the result into an FPR. Information about the

status of ﬂoating-point operations is placed into the FPSCR and in some cases, into the CR

after the completion of instruction execution.

The ﬂoating-point arithmetic instructions produce intermediate results that may be

regarded as inﬁnitely precise. After normalization or denormalization, if the precision of

the intermediate result cannot be represented in the destination format (single or double

precision), it is rounded to the speciﬁed precision before being placed in the target FPR.

The ﬁnal result is then placed into the FPR in the double-precision format.

Figure 3. Floating-Point Registers (FPRs)

1.3 XER Register (XER)

The XER register (XER) is shown in Figure 4.

Figure 4. XER Register

Table 5 provides bit setting information for XER.

Table 5. XER Bit Definitions

Bit(s) Name Description

0 SO Summary overﬂow. The summary overﬂow bit (SO) is set whenever an instruction (except

mtspr

)

sets the overﬂow bit (OV). Once set, the SO bit remains set until it is cleared by an

mtspr

instruction (specifying the XER) or an

mcrxr

instruction. It is not altered by compare instructions,

nor by other instructions (except

mtspr

to the XER, and

mcrxr

) that cannot overﬂow. Executing

mtspr

instruction to the XER, supplying the values zero for SO and one for OV, causes SO to

be cleared and OV to be set.

1 OV Overﬂow. The overﬂow bit (OV) is set to indicate that an overﬂow has occurred during execution

of an instruction. Add, subtract from, and negate instructions having OE = 1 set the OV bit if the

carry out of the msb is not equal to the carry out of the msb + 1, and clear it otherwise. Multiply

low and divide instructions having OE = 1 set the OV bit if the result cannot be represented in 64

bits (

mulld

divd

divdu

) or in 32 bits (

mullw

divw

divwu

), and clear it otherwise. The OV bit is

not altered by compare instructions that cannot overﬂow (except

mtspr

to the XER, and

mcrxr

0 63

FPR0

FPR1

. . .

FPR31

SOOV CA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Byte count

0 1 2 3 24 25 31

Reserved

PowerPC Microprocessor Family: The Programmer’s Reference Guide

1.4 Floating-Point Status and Control Register

(FPSCR)

Figure 5 shows the format of the ﬂoating-point status and control register (FPSCR).

Figure 5. Floating-Point Status and Control Register (FPSCR)

The FPSCR contains bits to do the following:

• Record exceptions generated by floating-point operations

• Record the type of the result produced by a floating-point operation

• Control the rounding mode used by floating-point operations

• Enable or disable the reporting of exceptions (invoking the exception handler)

Bits 0–23 are status bits. Bits 24–31 are control bits. Status bits in the FPSCR are updated

at the completion of the instruction execution.

Except for the ﬂoating-point enabled exception summary (FEX) and ﬂoating-point invalid

operation exception summary (VX), the exception condition bits in the FPSCR (bits 0–12

and 21–23) are sticky. Once set, sticky bits remain set until they are cleared by an

mcrfs

mtfsﬁ

mtfsf

, or

mtfsb0

instruction.

FEX and VX are the logical ORs of other FPSCR bits. Therefore, these two bits are not

listed among the FPSCR bits directly affected by the various instructions.

2 CA Carry. The carry bit (CA) is set during execution of the following instructions:

• Add carrying, subtract from carrying, add extended, and subtract from extended instructions

set CA if there is a carry out of the msb, and clear it otherwise.

• Shift right algebraic instructions set CA if any 1 bits have been shifted out of a negative

operand, and clear it otherwise.

The CA bit is not altered by compare instructions, nor by other instructions that cannot carry

(except shift right algebraic,

mtspr

to the XER, and

mcrxr

3–24 — Reserved

25–31 Byte

Count

This ﬁeld speciﬁes the number of bytes to be transferred by a Load String Word Indexed (

lswx

) or

Store String Word Indexed (

stswx

) instruction.

Table 5. XER Bit Definitions (Continued)

Bit(s) Name Description

0 1 2 3 4 5 6 7 8 9 101112131415 192021222324252627282930 31

VXIDI

VXISI

VXSNAN

VXZDZ

VXIMZ

VXVC

VXSOFT

VXSQRT

VXCVI

Reserved

FX FEXVX OX UX ZX XX FR FI FPRF 0 VE OE UE ZE XE NI RN

PowerPC Microprocessor Family: The Programmer’s Reference Guide

FPSCR bit settings are shown in Table 6.

Table 6. FPSCR Bit Settings

Bit(s) Name Description

0 FX Floating-point exception summary. Every ﬂoating-point instruction, except

mtfsﬁ

and

mtfsf

implicitly sets FPSCR[FX] if that instruction causes any of the ﬂoating-point exception bits in

the FPSCR to transition from 0 to 1. The

mcrfs

mtfsﬁ

mtfsf

mtfsb0

, and

mtfsb1

instructions can alter FPSCR[FX] explicitly. This is a sticky bit.

1 FEX Floating-point enabled exception summary. This bit signals the occurrence of any of the

enabled exception conditions. It is the logical OR of all the ﬂoating-point exception bits

masked by their respective enable bits. The

mcrfs

mtfsf

mtfsﬁ

mtfsb0

, and

mtfsb1

instructions cannot alter FPSCR[FEX] explicitly. This is not a sticky bit.

2 VX Floating-point invalid operation exception summary. This bit signals the occurrence of any

invalid operation exception. It is the logical OR of all of the invalid operation exceptions. The

mcrfs

mtfsf

mtfsﬁ

mtfsb0

, and

mtfsb1

instructions cannot alter FPSCR[VX] explicitly. This

is not a sticky bit.

3 OX Floating-point overﬂow exception. This is a sticky bit.

4 UX Floating-point underﬂow exception. This is a sticky bit.

5 ZX Floating-point zero divide exception. This is a sticky bit.

6 XX Floating-point inexact exception. This is a sticky bit.

FPSCR[XX] is the sticky version of FPSCR[FI]. The following rules describe how FPSCR[XX]

is set by a given instruction:

• If the instruction affects FPSCR[FI], the new value of FPSCR[XX] is obtained by logically

ORing the old value of FPSCR[XX] with the new value of FPSCR[FI].

• If the instruction does not affect FPSCR[FI], the value of FPSCR[XX] is unchanged.

7 VXSNAN Floating-point invalid operation exception for SNaN. This is a sticky bit.

8 VXISI Floating-point invalid operation exception for

∞

–

∞

. This is a sticky bit.

9 VXIDI Floating-point invalid operation exception for ∞ ÷ ∞. This is a sticky bit.

10 VXZDZ Floating-point invalid operation exception for 0 ÷ 0. This is a sticky bit.

11 VXIMZ Floating-point invalid operation exception for ∞ * 0. This is a sticky bit.

12 VXVC Floating-point invalid operation exception for invalid compare. This is a sticky bit.

13 FR Floating-point fraction rounded. The last arithmetic or rounding and conversion instruction that

rounded the intermediate result incremented the fraction. This bit is not sticky.

14 FI Floating-point fraction inexact. The last arithmetic or rounding and conversion instruction

either rounded the intermediate result (producing an inexact fraction) or caused a disabled

overﬂow exception. This is not a sticky bit. For more information regarding the relationship

between FPSCR[FI] and FPSCR[XX], see the description of the FPSCR[XX] bit.

PowerPC Microprocessor Family: The Programmer’s Reference Guide 11

Table 7 illustrates the ﬂoating-point result ﬂags used by PowerPC processors. The result

ﬂags correspond to FPSCR bits 15–19.

15–19 FPRF Floating-point result ﬂags. For arithmetic, rounding, and conversion instructions the ﬁeld is

based on the result placed into the target register, except that if any portion of the result is

undeﬁned, the value placed here is undeﬁned.

15 Floating-point result class descriptor (C). Arithmetic, rounding and conversion

instructions may set this bit with the FPCC bits to indicate the class of the result;

see Table 7.

16–19 Floating-point condition code (FPCC). Floating-point compare instructions always

set one of the FPCC bits to one and the other three FPCC bits to zero. Arithmetic,

rounding and conversion instructions may set the FPCC bits with the C bit to

indicate the class of the result. Note that in this case the high-order three bits of the

FPCC retain their relational signiﬁcance indicating that the value is less than,

greater than, or equal to zero.

16 Floating-point less than or negative (FL or <)

17 Floating-point greater than or positive (FG or >)

18 Floating-point equal or zero (FE or =)

19 Floating-point unordered or NaN (FU or ?)

These are not sticky bits.

20 — Reserved

21 VXSOFT Floating-point invalid operation exception for software request. This is a sticky bit. This bit can

be altered only by the mcrfs, mtfsﬁ, mtfsf, mtfsb0, or mtfsb1 instructions.

22 VXSQRT Floating-point invalid operation exception for invalid square root. This is a sticky bit.

23 VXCVI Floating-point invalid operation exception for invalid integer convert. This is a sticky bit.

24 VE Floating-point invalid operation exception enable. This is not a sticky bit.

25 OE IEEE ﬂoating-point overﬂow exception enable. This is not a sticky bit.

26 UE IEEE ﬂoating-point underﬂow exception enable. This is not a sticky bit.

27 ZE IEEE ﬂoating-point zero divide exception enable. This is not a sticky bit.

28 XE Floating-point inexact exception enable. This is not a sticky bit.

29 NI Floating-point non-IEEE mode. If this bit is set, results need not conform with IEEE standards

and the other FPSCR bits may have meanings other than those described here. If the bit is set

and if all implementation-speciﬁc requirements are met and if an IEEE-conforming result of a

ﬂoating-point operation would be a denormalized number, the result produced is zero

(retaining the sign of the denormalized number). Any other effects associated with setting this

bit are described in the user’s manual for the implementation.

Effects of the setting of this bit is implementation-dependent. This is not a sticky bit.

30–31 RN Floating-point rounding control.

00 Round to nearest

01 Round toward zero

10 Round toward +inﬁnity

11 Round toward –inﬁnity

These are not sticky bits.

Table 6. FPSCR Bit Settings (Continued)

Bit(s) Name Description

12 PowerPC Microprocessor Family: The Programmer’s Reference Guide

1.5 Condition Register (CR)

The format of the condition register (CR) is shown in Figure 6.

Figure 6. Condition Register (CR)

The CR ﬁelds can be set in one of the following ways:

• Specified fields of the CR can be set by a move instruction (mtcrf) to the CR from

a GPR.

• A specified field of the CR can be moved to another CR field with the mcrf

instruction.

• A specified field of the XER can be copied to the CR by the mcrxr instruction.

• A specified field of the FPSCR can be copied to the CR by the mcrfs instruction.

• Condition register logical instructions can be used to perform logical operations on

specified bits in the condition register.

• CR0 can be the implicit result of an integer instruction.

• CR1 can be the implicit result of a floating-point instruction.

• A speciﬁed CR ﬁeld can indicate the result of either an integer or ﬂoating-point

compare instruction.

Note that branch instructions are provided to test individual CR bits.

Table 7. Floating-Point Result Flags in FPSCR

Result Flags (Bits 15–19)

Result Value Class

C<>=?

10001Quiet NaN

01001–Inﬁnity

01000–Normalized number

11000–Denormalized number

10010–Zero

00010+Zero

10100+Denormalized number

00100+Normalized number

00101+Inﬁnity

CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7

0 3 4 7 8 1112 1516 19 20 2324 2728 31

PowerPC Microprocessor Family: The Programmer’s Reference Guide 13

The following tables, Table 8–Table 10, provide bit setting information for CR0, CR1, and

the CRn fields, respectively.

Table 8. Bit Settings for CR0 Field of CR

CR0

Bit

Description

0 Negative (LT)—This bit is set when the result is negative.

1 Positive (GT)—This bit is set when the result is positive (and not zero).

2 Zero (EQ)—This bit is set when the result is zero.

3 Summary overﬂow (SO)—This is a copy of the ﬁnal state of XER[SO] at

the completion of the instruction.

Table 9. Bit Settings for CR1 Field of CR

CR1

Bit

Description

4 Floating-point exception (FX)—This is a copy of the ﬁnal state of

FPSCR[FX] at the completion of the instruction.

5 Floating-point enabled exception (FEX)—This is a copy of the ﬁnal

state of FPSCR[FEX] at the completion of the instruction.

6 Floating-point invalid exception (VX)—This is a copy of the ﬁnal state

of FPSCR[VX] at the completion of the instruction.

7 Floating-point overﬂow exception (OX)—This is a copy of the ﬁnal

state of FPSCR[OX] at the completion of the instruction.

Note: For more information on the FPSCR refer to Section 1.4, “Floating-Point

Status and Control Register (FPSCR).”

14 PowerPC Microprocessor Family: The Programmer’s Reference Guide

1.6 Link Register (LR)

The link register (LR) is a 64-bit register in 64-bit implementations and a 32-bit register in

32-bit implementations. The LR supplies the branch target address for the Branch

Conditional to Link Register (bclrx) instruction, and can be used to hold the logical address

of the instruction that follows a branch and link instruction. The format of LR is shown in

Figure 7.

Figure 7. Link Register (LR)

Note that although the two least-signiﬁcant bits can accept any values written to them, they

are ignored when the LR is used as an address. The link register can be accessed by the

mtspr and mfspr instructions using SPR8. Fetching instructions along the target path

(loaded by an mtspr instruction) is possible provided the link register is loaded sufﬁciently

ahead of the branch instruction. It is possible for a PowerPC microprocessor to fetch along

a target path loaded by a branch and link instruction.

Both conditional and unconditional branch instructions include the option of placing the

effective address of the instruction following the branch instruction in the LR.

Table 10. CR

Field Bit Settings for Compare Instructions

Bit

Description

0 Less than or ﬂoating-point less than (LT, FL).

For integer compare instructions: rA < SIMM or rB (signed comparison) or

rA < UIMM or rB (unsigned comparison).

For ﬂoating-point compare instructions: frA < frB.

1 Greater than or ﬂoating-point greater than (GT, FG).

For integer compare instructions: rA > SIMM or rB (signed comparison) or

rA > UIMM or rB (unsigned comparison).

For ﬂoating-point compare instructions: frA > frB.

2 Equal or ﬂoating-point equal (EQ, FE).

For integer compare instructions: rA = SIMM, UIMM, or rB.

For ﬂoating-point compare instructions: frA = frB.

3 Summary overﬂow or ﬂoating-point unordered (SO, FU).

For integer compare instructions: This is a copy of the ﬁnal state of XER[SO]

at the completion of the instruction.

For ﬂoating-point compare instructions: One or both of frA and frB is a Not a

Number (NaN).

Notes:

1. Here, the bit indicates the bit number in any one of the four-bit subﬁelds, CR0–CR7.

2. For a complete description of instruction syntax conventions, refer to Table 31.

Branch Address

0 63/31

PowerPC Microprocessor Family: The Programmer’s Reference Guide 15

1.7 Count Register (CTR)

The count register (CTR) is a 64-bit register in 64-bit implementations and a 32-bit register

in 32-bit implementations. The CTR can hold a loop count that can be decremented during

execution of branch instructions that contain an appropriately coded BO ﬁeld. If the value

in CTR is 0 before being decremented, it is –1 afterward. The CTR can also provide the

branch target address for the Branch Conditional to Count Register (bcctrx) instruction.

The CTR is shown in Figure 8.

Figure 8. Count Register (CTR)

Fetching instructions along the target path is also possible provided the count register is

loaded sufﬁciently ahead of the branch instruction.

The count register can be accessed by the mtspr and mfspr instructions by specifying

SPR9. In branch conditional instructions, the BO ﬁeld speciﬁes the conditions under which

the branch is taken. The ﬁrst four bits of the BO ﬁeld specify how the branch is affected by

or affects the CR and the CTR. The encoding for the BO ﬁeld is shown in Table 11.

Table 11. BO Operand Encodings

BO Description

0000

Decrement the CTR, then branch if the decremented CTR ≠ 0 and the condition is FALSE.

0001

Decrement the CTR, then branch if the decremented CTR = 0 and the condition is FALSE.

001

Branch if the condition is FALSE.

0100

Decrement the CTR, then branch if the decremented CTR ≠ 0 and the condition is TRUE.

0101

Decrement the CTR, then branch if the decremented CTR = 0 and the condition is TRUE.

011

Branch if the condition is TRUE.

Decrement the CTR, then branch if the decremented CTR ≠ 0.

Decrement the CTR, then branch if the decremented CTR = 0.

Branch always.

The

indicates a bit that is ignored. The

bits should be cleared to zero, as they may be assigned a

meaning in some future version of the PowerPC architecture.

The

bit provides a hint about whether a conditional branch is likely to be taken and is used by some

PowerPC implementations to improve performance. Other implementations may ignore the

bit.

CTR

0 63/31

16 PowerPC Microprocessor Family: The Programmer’s Reference Guide

1.8 Machine State Register (MSR)

The machine state register (MSR), is a 64-bit register on 64-bit implementations (see

Figure 9) and a 32-bit register in 32-bit implementations (see Figure 10).

Figure 9. Machine State Register (MSR)—64-bit Implementations

Figure 10. Machine State Register (MSR)—32-bit Implementations

Table 12 shows the bit deﬁnitions for the MSR. Full function reserved bits are saved in

SRR1 when an exception occurs; partial function reserved bits are not saved.

Table 12. MSR Bit Settings

Bit(s)

Name Description

64 Bit 32 Bit

0 — SF Sixty-four bit mode

0 The 64-bit processor runs in 32-bit mode.

1 The 64-bit processor runs in 64-bit mode. Note that this is the default setting.

1–32 0 — Reserved. Full function.

33–36 1–4 — Reserved. Partial function.

37–41 5–9 — Reserved. Full function.

42–44 10–12 — Reserved. Partial function.

45 13 POW Power management enable

0 Power management disabled (normal operation mode).

1 Power management enabled (reduced power mode).

Note: Power management functions are implementation-dependent. If the function

is not implemented, this bit is treated as reserved.

46 14 — Reserved—Implementation-speciﬁc

47 15 ILE Exception little-endian mode. When an exception occurs, this bit is copied into

MSR[LE] to select the endian mode for the context established by the exception.

48 16 EE External interrupt enable

0 While the bit is cleared the processor delays recognition of external interrupts

and decrementer exception conditions.

1 The processor is enabled to take an external interrupt or the decrementer

exception.

0 1 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 6162 63

SF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POW 0 ILE EE PR FPMEFE0 SE BE FE1 0 IP IR DR 0 0 RI LE

Reserved

01213141516171819202122232425262728293031

0 0 0 0 0 0 0 0 0 0 0 0 0

POW 0 ILE EE PR FP MEFE0 SE BE FE1 0 IP IR DR 0 0 RI LE

Reserved

PowerPC Microprocessor Family: The Programmer’s Reference Guide 17

49 17 PR Privilege level

0 The processor can execute both user- and supervisor-level instructions.

1 The processor can only execute user-level instructions.

50 18 FP Floating-point available

0 The processor prevents dispatch of ﬂoating-point instructions, including

ﬂoating-point loads, stores, and moves.

1 The processor can execute ﬂoating-point instructions.

51 19 ME Machine check enable

0 Machine check exceptions are disabled.

1 Machine check exceptions are enabled.

52 20 FE0 Floating-point exception mode 0 (see Table 13).

53 21 SE Single-step trace enable (Optional)

0 The processor executes instructions normally.

1 The processor generates a single-step trace exception upon the successful

execution of the next instruction.

Note: If the function is not implemented, this bit is treated as reserved.

54 22 BE Branch trace enable (Optional)

0 The processor executes branch instructions normally.

1 The processor generates a branch trace exception after completing the

execution of a branch instruction, regardless of whether or not the branch was

taken.

Note: If the function is not implemented, this bit is treated as reserved.

55 23 FE1 Floating-point exception mode 1 (see Table 13).

56 24 — Reserved. Full function.

57 25 IP Exception preﬁx. The setting of this bit speciﬁes whether an exception vector offset

is prepended with Fs or 0s. In the following description,

nnnnn

is the offset of the

exception. See Table 30.

0 Exceptions are vectored to the physical address 0x000

n_nnnn

in 32-bit

implementations and 0x0000_0000_000

nnnn

in 64-bit implementations.

1 Exceptions are vectored to the physical address 0xFFF

n_nnnn

in 32-bit

implementations and 0xFFFF_FFFF_FFF

nnnn

in 64-bit implementations.

58 26 IR Instruction address translation

0 Instruction address translation is disabled.

1 Instruction address translation is enabled.

59 27 DR Data address translation

0 Data address translation is disabled.

1 Data address translation is enabled.

60–61 28–29 — Reserved. Full function.

62 30 RI Recoverable exception (for system reset and machine check exceptions).

0 Exception is not recoverable.

1 Exception is recoverable.

63 31 LE Little-endian mode enable

0 The processor runs in big-endian mode.

1 The processor runs in little-endian mode.

Table 12. MSR Bit Settings (Continued)

Bit(s)

Name Description

64 Bit 32 Bit

18 PowerPC Microprocessor Family: The Programmer’s Reference Guide

The ﬂoating-point exception mode bits (FE0–FE1) are interpreted as shown in Table 13.

Note that these bits can be logically ORed, so that if either is set the processor operates in

precise mode.

Table 14 indicates the initial state of the MSR.

Table 13. Floating-Point Exception Mode Bits

FE0 FE1 Mode

0 0 Floating-point exceptions disabled

0 1 Floating-point imprecise nonrecoverable

1 0 Floating-point imprecise recoverable

1 1 Floating-point precise mode

Table 14. State of MSR at Power Up

Bit(s)

Name

64-Bit

Description

32-Bit

Description

64 Bit 32 Bit

0—SF1 —

1–44 0–12 — Unspeciﬁed

Unspeciﬁed

45 13 POW 0 0

46 14 — Unspeciﬁed

Unspeciﬁed

47 15 ILE 0 0

48 16 EE 0 0

49 17 PR 0 0

50 18 FP 0 0

51 19 ME 0 0

52 20 FE0 0 0

53 21 SE 0 0

54 22 BE 0 0

55 23 FE1 0 0

56 24 — Unspeciﬁed

Unspeciﬁed

57 25 IP 1

58 26 IR 0 0

59 27 DR 0 0

PowerPC Microprocessor Family: The Programmer’s Reference Guide 19

1.9 Processor Version Register (PVR)

The processor version register (PVR) is a 32-bit, read-only register that contains a value

identifying the speciﬁc version (model) and revision level of the PowerPC processor (see

Figure 11). The contents of the PVR can be copied to a GPR by the mfspr instruction. Read

access to the PVR is supervisor-level only; write access is not provided.

Figure 11. Processor Version Register (PVR)

The PVR consists of two 16-bit ﬁelds:

• Version (bits 0–15)—A 16-bit number that uniquely determines a particular

processor version and version of the PowerPC architecture. This number can be used

to determine the version of a processor; it may not distinguish between different

product models if more than one model uses the same processor.

• Revision (bits 16–31)—A 16-bit number that distinguishes between various releases

of a particular version (that is, an engineering change level). The value of the

revision portion of the PVR is implementation-speciﬁc. The processor revision level

is changed for each revision of the device.

60–61 28–29 — Unspeciﬁed

Unspeciﬁed

62 30 RI 0 0

63 31 LE 0 0

Notes:

1. Unspeciﬁed can be either 0 or 1

2. 1 is typical, but might be 0

Table 14. State of MSR at Power Up (Continued)

Bit(s)

Name

64-Bit

Description

32-Bit

Description

64 Bit 32 Bit

0151631

Version Revision

20 PowerPC Microprocessor Family: The Programmer’s Reference Guide

1.10 BAT Registers

Figure 12 and Figure 13 show the format of the upper and lower BAT registers for 64-bit

PowerPC processors.

Figure 12. Upper BAT Register—64-Bit Implementations

Figure 13. Lower BAT Register—64-Bit Implementations

Figure 14 and Figure 15 show the format of the upper and lower BAT registers for 32-bit

PowerPC processors.

Figure 14. Format of Upper BAT Registers—32-Bit Implementations

Figure 15. Format of Lower BAT Registers—32-Bit Implementations

046475051616263

BEPI 0 0 0 0 BL Vs Vp

Reserved

BRPN 0 0 0 0 0 0 0 0 0 0 WIMG 0 PP

0 4647 5657 60 6162 63

Reserved

BEPI 0 0 0 0 BL Vs Vp

014151819293031

Reserved

01415242528293031

BRPN 0 0 0 0 0 0 0 0 0 0 WIMG 0 PP

Reserved

PowerPC Microprocessor Family: The Programmer’s Reference Guide 21

Table 15 describes the bits in the BAT registers.

Table 16 lists the BAT area lengths encoded in the BL ﬁeld of the upper BAT registers.

Table 15. BAT Registers—Field and Bit Descriptions

Upper/

Lower

BAT

Bits

Name Description

64 Bit 32 Bit

Upper

BAT

0–46 0–14 BEPI Block effective page index. This ﬁeld is compared with high-order bits

of the logical address to determine if there is a hit in that BAT array

entry. (The architecture speciﬁcation refers to logical address as

effective address.)

46–50 15–18 — Reserved

51–61 19–29 BL Block length. BL is a mask that encodes the size of the block. Values

for this ﬁeld are listed in Table 16.

62 30 Vs Supervisor mode valid bit. This bit interacts with MSR[PR] to

determine if there is a match with the logical address.

63 31 Vp User mode valid bit. This bit also interacts with MSR[PR] to

determine if there is a match with the logical address.

Lower

BAT

0–46 0–14 BRPN This ﬁeld is used in conjunction with the BL ﬁeld to generate high-

order bits of the physical address of the block.

47–56 15–24 — Reserved

57–60 25–28 WIMG Memory/cache access mode bits

W Write-through

I Caching-inhibited

M Memory coherence

G Guarded

61 29 — Reserved

62–63 30–31 PP Protection bits for block

Table 16. BAT Area Lengths

BAT Area

Length

BL Encoding

128 Kbytes 000 0000 0000

256 Kbytes 000 0000 0001

512 Kbytes 000 0000 0011

1 Mbyte 000 0000 0111

2 Mbytes 000 0000 1111

4 Mbytes 000 0001 1111

8 Mbytes 000 0011 1111

16 Mbytes 000 0111 1111

32 Mbytes 000 1111 1111

22 PowerPC Microprocessor Family: The Programmer’s Reference Guide

1.11 SDR1

The SDR1 is a 64-bit register in 64-bit implementations and a 32-bit register in 32-bit

implementations. Refer to Section 2.3.3, “SDR1 Register Deﬁnitions,” for a complete

description of SDR1.

1.12 Address Space Register (ASR)

The address space register (ASR) is a 64-bit SPR that holds 0–51 of the segment table’s

physical address. The segment table is the segment descriptor mechanism for 64-bit

implementations. For more detailed information about the ASR, refer to Section 2.2.1.1,

“Address Space Register (ASR).”

1.13 Segment Registers (SRs)

Segment registers are used in page and direct-store segment address translations. Refer to

Section 2.2, “Segment Descriptor Deﬁnitions,” for information on segment registers.

1.14 Data Address Register (DAR)

The DAR is a 64-bit register in 64-bit implementations and a 32-bit register in 32-bit

implementations. The DAR is shown in Figure 16.

Figure 16. Data Address Register (DAR)

The effective address generated by a memory access instruction is placed in the DAR if the

access causes an exception (for example, an alignment exception). If the exception occurs

in a 64-bit implementation operating in 32-bit mode, the high-order 32 bits of the DAR are

cleared.

64 Mbytes 001 1111 1111

128 Mbytes 011 1111 1111

256 Mbytes 111 1111 1111

Table 16. BAT Area Lengths (Continued)

BAT Area

Length

BL Encoding

DAR

0 63

PowerPC Microprocessor Family: The Programmer’s Reference Guide 23

1.15 SPRG0–SPRG3

SPRG0–SPRG3 are 64-bit or 32-bit registers, depending on the type of PowerPC

microprocessor. They are provided for general operating system use, such as performing a

fast state save or for supporting multiprocessor implementations. The formats of SPRG0

through SPRG3 are shown in Figure 17.

Figure 17. SPRG0–SPRG3

Table 17 provides a description of conventional uses of SPRG0–SPRG3.

1.16 DSISR

The 32-bit DSISR, shown in Figure 18, identiﬁes the cause of DSI and alignment

exceptions.

Figure 18. DSISR

1.17 Machine Status Save/Restore Register 0 (SRR0)

The SRR0 is a 64-bit register in 64-bit implementations and a 32-bit register in 32-bit

implementations. SRR0 is used to save machine status on exceptions and restore machine

Table 17. Conventional Uses of SPRG0–SPRG3

SPRG0 Software may load a unique physical address in this register to identify an area of memory

reserved for use by the ﬁrst-level exception handler. This area must be unique for each processor

in the system.

SPRG1 This register may be used as a scratch register by the ﬁrst-level exception handler to save the

content of a GPR. That GPR then can be loaded from SPRG0 and used as a base register to

save other GPR’s to memory.

SPRG2 This register may be used by the operating system as needed.

SPRG3 This register may be used by the operating system as needed.

0 63

SPRG0

SPRG1

SPRG2

SPRG3

0 63

DSISR

0 31

24 PowerPC Microprocessor Family: The Programmer’s Reference Guide

status when an rﬁ instruction is executed. It also holds the EA for the instruction that

follows the System Call (sc) instruction. The format of SRR0 is shown in Figure 19. For

32-bit implementations, the format of SRR0 follows the low-order bits (32–63) of

Figure 19.

Figure 19. Machine Status Save/Restore Register 0 (SRR0)

When an exception occurs, SRR0 is set to point to an instruction such that all prior

instructions have completed execution and no subsequent instruction has begun execution.

When rﬁ is executed, the contents of SRR0 are copied to the next instruction address

(NIA)—the 64- or 32-bit address of the next instruction to be executed. The instruction

addressed by SRR0 may not have completed execution, depending on the exception type.

SRR0 addresses either the instruction causing the exception or the instruction that

immediately follows. The instruction addressed can be determined from the exception type

and status bits.

If the exception occurs in 32-bit mode of the 64-bit implementation, the high-order 32 bits

of SRR0 are cleared and the high-order 32 bits of the NIA are cleared when returning to

32-bit mode.

Note that in some implementations, every instruction fetch, when MSR[IR] = 1, and every

instruction execution requiring address translation when MSR[DR] = 1, may modify

SRR0.

1.18 Machine Status Save/Restore Register 1 (SRR1)

The SRR0 is a 64-bit register in 64-bit implementations and a 32-bit register in 32-bit

implementations. SRR1 is used to save machine status on exceptions and to restore

machine status when an rﬁ instruction is executed. The format of SRR1 is shown in

Figure 20.

Figure 20. Machine Status Save/Restore Register 1 (SRR1)

On 64-bit implementations, when an exception occurs, bits 33–36 and 42–47 of SRR1 are

loaded with exception-speciﬁc information and bits 0–32, 37–41, and 48–63 of MSR are

placed into the corresponding bit positions of SRR1.

SRR0

0 61 62 63

0 0

Reserved

SRR1

0 63

PowerPC Microprocessor Family: The Programmer’s Reference Guide 25

For 32-bit implementations, when an exception occurs, bits 1–4 and 10–15 of SRR1 are

loaded with exception-speciﬁc information and bits 0, 5–9, and 16–31 of MSR are placed

into the corresponding bit positions of SRR1.

Note that, in some implementations, every instruction fetch when MSR[IR] = 1, and every

instruction execution requiring address translation when MSR[DR] = 1, may modify

SRR1.

1.19 Time Base Facility (TB)

The time base (TB), shown in Figure 21, is a 64-bit structure that contains a 64-bit unsigned

integer that is incremented periodically. Each increment adds 1 to the low-order bit (bit 63).

The frequency at which the counter is incremented is implementation-dependent.

Figure 21. Time Base (TB)

The TB increments until its value becomes 0xFFFF_FFFF_FFFF_FFFF (2

– 1). At the

next increment its value becomes 0x0000_0000_0000_0000. Note that there is no explicit

indication that this has occurred (that is, no exception is generated).

The period of the time base depends on the driving frequency. The TB is implemented such

that the following requirements are satisﬁed:

1. Loading a GPR from the time base has no effect on the accuracy of the time

base.

2. Storing a GPR to the time base replaces the value in the time base with the value in

the GPR.

The PowerPC VEA does not specify a relationship between the frequency at which the time

base is updated and other frequencies, such as the processor clock. The TB update

frequency is not required to be constant; however, for the system software to maintain time

of day and operate interval timers, one of two things is required:

• The system provides an implementation-dependent exception to software whenever

the update frequency of the time base changes and a means to determine the current

update frequency; or

• The system software controls the update frequency of the time base.

Note that if the operating system initializes the TB to some ‘reasonable’ value and the

update frequency of the TB is constant, the TB can be used as a source of values that

increase at a constant rate, such as for time stamps in trace entries.

031031

TBU—Upper 32 bits of time base

TBL—Lower 32 bits of time base

26 PowerPC Microprocessor Family: The Programmer’s Reference Guide

Even if the update frequency is not constant, values read from the TB are monotonically

increasing (except when the TB wraps from 2

– 1 to 0). If a trace entry is recorded each

time the update frequency changes, the sequence of TB values can be post-processed to

become actual time values.

For information on reading, writing, and computing time of day on the time base, refer to

Chapter 2, “PowerPC Register Set,” The Programming Environments Manual.

1.20 Decrementer Register (DEC)

The DEC, shown in Figure 22, is a 32-bit decrementing counter that provides a mechanism

for causing a decrementer exception after a programmable delay. The DEC frequency is

based on the same implementation-dependent frequency that drives the time base.

Figure 22. Decrementer Register (DEC)

For information on writing and reading the DEC, refer to Chapter 2, “PowerPC Register

Set,” The Programming Environments Manual.

1.21 Data Address Breakpoint Register (DABR)

The data address breakpoint facility is controlled by the DABR, a 64-bit register in 64-bit

implementations and a 32-bit register in 32-bit implementations. The data address

breakpoint facility is optional to the PowerPC architecture, as is the DABR. However, if

the data address breakpoint facility is implemented, it is recommended, but not required,

that it be implemented as described in this section.

The data address breakpoint facility provides a means to detect accesses to a designated

double word. The address comparison is done on an effective address, and it applies to data

accesses only. It does not apply to instruction fetches.

The DABR is shown in Figure 23.

Figure 23. Data Address Breakpoint Register—64-Bit Implementations

DEC

0 31

0 60 61 62 63

DAB BT DW DR

PowerPC Microprocessor Family: The Programmer’s Reference Guide 27

Table 18 describes the ﬁelds in the DABR.

A data address breakpoint match is detected for a load or store instruction if the three

following conditions are met for any byte accessed:

• EA[0–60] = DABR[DAB]

• MSR[DR] = DABR[BT]

• The instruction is a store and DABR[DW] = 1, or the instruction is a load and

DABR[DR] = 1.

In 32-bit mode of a 64-bit implementation, the high-order 32 bits of the EA are treated as

zero for the purpose of detecting a match.

1.22 External Access Register (EAR)

The EAR is an optional 32-bit SPR that controls access to the external control facility and

identiﬁes the target device for external control operations. The external control facility

provides a means for user-level instructions to communicate with special external devices.

The EAR is shown in Figure 24. Note that the EAR is an optional register.

Figure 24. External Access Register (EAR)

The high-order bits of the resource ID (RID) ﬁeld that correspond to bits of the RID beyond

the width of the RID supported by a particular implementation are treated as reserved bits.

The EAR register is provided to support the External Control In Word Indexed (eciwx) and

External Control Out Word Indexed (ecowx) instructions. Access to the EAR is supervisor-

level, thus the operating system can determine which tasks are allowed to issue external

access instructions and when they are allowed to do so. The bit settings for the EAR are

described in Table 19.

Table 18. DABR—Field Descriptions

Bits

Name Description

64 Bit 32 Bit

0–60 0–28 DAB Data address breakpoint

61 29 BT Breakpoint translation enable

62 30 DW Data write enable

63 31 DR Data read enable

01 25 26 31

E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RID

Reserved

28 PowerPC Microprocessor Family: The Programmer’s Reference Guide

The data access of eciwx and ecowx is performed as though the memory access mode bits

(WIMG) were 0101. For example, if the external control facility is used to support a

graphics adapter, the ecowx instruction could be used to send the translated physical

address of a buffer containing graphics data to the graphics device. The eciwx instruction

could be used to load status information from the graphics adapter.

This register can also be accessed by using the mtspr and mfspr instructions.

Part 2 Memory Control Model

Memory in the PowerPC OEA is divided into 256-Mbyte segments. This segmented

memory model provides a way to map 4-Kbyte pages of effective addresses to 4-Kbyte

pages in physical memory (page address translation), while providing the programming

ﬂexibility afforded by a large virtual address space (80 or 52 bits).

The page address translation uses segment descriptors, which provide virtual address and

protection information, and page table entries (PTEs), which provide the physical address

and page protection information. The segment descriptors are programmed by the

operating system to provide the virtual ID for a segment. In addition, the operating system

also creates the page tables in memory that provide the virtual to physical address mappings

(in the form of PTEs) for the pages in memory.

Segments in the OEA are deﬁned as one of the following two types:

• Memory segment—An effective address in these segments represents a virtual

address that is used to define the physical address of the page.

• Direct-store segment—References made to direct-store segments do not use the

virtual paging mechanism of the processor.

The T bit in the segment descriptor selects between memory segments and direct-store

segments, as shown in Table 20.

Table 19. External Access Register (EAR) Bit Settings

Bit Name Description

0 E Enable bit

1 Enabled

0 Disabled

If this bit is set, the eciwx and ecowx instructions can perform the

speciﬁed external operation. If the bit is cleared, an eciwx or ecowx

instruction causes a DSI exception.

1–25 — Reserved

26–31 RID Resource ID

PowerPC Microprocessor Family: The Programmer’s Reference Guide 29

All accesses generated by the processor map to a segment descriptor. If MSR[IR] = 0 or

MSR[DR] = 0 for an instruction or data access, respectively, then real addressing mode

translation is performed. Otherwise, if T = 0 in the corresponding segment descriptor (and

the address is not translated by the BAT mechanism), the access maps to memory space and

page address translation is performed.

After a memory segment is selected, the processor creates the virtual address for the

segment and searches for the PTE that dictates the physical page number to be used for the

access. Note that I/O devices can be easily mapped into memory space and used as

memory-mapped I/O.

2.1 Address Translation Overview

The following sections provide a brief overview of the page and direct-store segment

address translation. For more information, refer to Chapter 7, “Memory Management,” in

The Programming Environments Manual.

2.1.1 Page Address Translation

The ﬁrst step in page address translation for 64-bit implementations is the conversion of the

64-bit effective address of an access into the 80-bit virtual address. The virtual address is

then used to locate the PTE in the page tables in memory. The physical page number is then

extracted from the PTE and used in the formation of the physical address of the access.

The translation of an effective address to a physical address for 64-bit implementations is

described brieﬂy:

• Bits 0–35 of the effective address comprise the effective segment ID used to select

a segment descriptor, from which the virtual segment ID (VSID) is extracted.

• Bits 36–51 of the effective address correspond to the page number within the

segment; these are concatenated with the VSID from the segment descriptor to form

the virtual page number (VPN). The VPN is used to search for the PTE in either an

on-chip TLB or the page table. The PTE then provides the physical page number

(RPN).

• Bits 52–63 of the effective address are the byte offset within the page; these are

concatenated with the RPN ﬁeld of a PTE to form the physical address used to

access memory.

Table 20. Segment Descriptor Types

Segment Descriptor

T Bit

Segment Type

0 Memory segment

1 Direct-store segment

30 PowerPC Microprocessor Family: The Programmer’s Reference Guide

The translation of effective addresses to physical addresses for 32-bit implementations is

similar to that for 64-bit implementations, except that 32-bit implementations index into an

array of 16 segment registers instead of segment tables in memory to locate the segment

descriptor, and the address ranges are obviously different. Thus, the address translation is

as follows:

• Bits 0–3 of the effective address comprise the segment register number used to

select a segment descriptor, from which the virtual segment ID (VSID) is extracted.

• Bits 4–19 of the effective address correspond to the page number within the

segment; these are concatenated with the VSID from the segment descriptor to form

the virtual page number (VPN). The VPN is used to search for the PTE in either an

on-chip TLB or the page table. The PTE then provides the physical page number

(RPN).

• Bits 20–31 of the effective address are the byte offset within the page; these are

concatenated with the RPN ﬁeld of a PTE to form the physical address used to

access memory.

2.1.2 Direct-Store Segment Address Translation

As described for memory segments, all accesses generated by the processor (with

translation enabled) that do not map to a BAT area, map to a segment descriptor. If T = 1

for the selected segment descriptor, the access maps to the direct-store interface, invoking

a speciﬁc bus protocol for accessing some special-purpose I/O devices. Direct-store

segments are provided for POWER compatibility. As the direct-store interface is present

only for compatibility with existing I/O devices that used this interface and the direct-store

interface protocol is not optimized for performance, its use is discouraged. Applications

that require low-latency load/store access to external address space should use memory-

mapped I/O, rather than the direct-store interface.

2.2 Segment Descriptor Deﬁnitions

The format of the segment descriptors is different for 64-bit and 32-bit implementations.

Additionally, the ﬁelds in the segment descriptors are interpreted differently depending on

the value of the T bit within the descriptor. When T = 1, the segment descriptor deﬁnes a

direct-store segment.

2.2.1 STE Format—64-Bit Implementations

In 64-bit implementations, the segment descriptors reside as segment table entries (STEs)

in hashed segment tables in memory. These STEs are generated and placed in segment

tables in memory by the operating system. Each STE is a 128-bit entity (two double words)

that maps one effective segment ID to one virtual segment ID. Information in the STE

controls the segment table search process and provides input to the memory protection

PowerPC Microprocessor Family: The Programmer’s Reference Guide 31

mechanism. Figure 25 shows the format of both double words that comprise a T = 0

segment descriptor (or STE) in a 64-bit implementation.

Figure 25. STE Format—64-Bit Implementations

Table 21 lists the bit deﬁnitions for each double word in an STE.

The Ks and Kp bits partially deﬁne the access protection for the pages within the segment.

The virtual segment ID ﬁeld is used as the high-order bits of the virtual page number

(VPN).

The segment descriptors are programmed by the operating system and placed into segment

tables in memory, although some processors may additionally have on-chip segment

lookaside buffers (SLBs). These SLBs store copies of recently-used STEs that can be

accessed quickly, providing increased overall performance.

2.2.1.1 Address Space Register (ASR)

The ASR contains the control information for the segment table structure in that it deﬁnes

the highest order bits for the physical base address of the segment table. The format of the

Table 21. STE Bit Definitions for Page Address Translation—64-Bit

Implementations

Double

Word

Bit Name Description

0 0–35 ESID Effective segment ID

36–55 — Reserved

56 V Entry valid (V = 1) or invalid (V = 0)

57 T T = 0 selects this format

58 Ks Supervisor-state protection key

59 Kp User-state protection key

60 N No-execute protection bit

61–63 — Reserved

1 0–51 VSID Virtual segment ID

52–63 — Reserved

Reserved

0 3536 55565758596061 63

0515263

ESID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V T Ks Kp N 0 0 0

VSID 0 0 0 0 0 0 0 0 0 0 0

32 PowerPC Microprocessor Family: The Programmer’s Reference Guide

ASR is shown in Figure 26. The ASR contains bits 0–51 of the 64-bit physical base address

of the segment table. Bits 52–56 of the STEG address are derived from the hashing

function, (and bits 57–63 are zero at the beginning of a segment table search operation to

point to the beginning of an STEG). Therefore, the beginning of the segment table lies on

a 2

byte (4 Kbyte) boundary.

Note that unless all accesses to be performed by the processor can be translated by the BAT

mechanism when address translation is enabled (MSR[DR] or MSR[IR] = 1), the ASR must

point to a valid segment table. If the processor does not support 64 bits of physical address,

software should write zeros to those unsupported bits in the ASR. Otherwise, a machine

check exception can occur.

Additionally, values x0, 0x1000, and 0x2000 should not be used as segment table addresses

as they correspond to areas of the exception vector table reserved for implementation-

speciﬁc purposes.

Figure 26. ASR Register Format—64-Bit Implementations Only

2.2.2 Segment Descriptor Format—32-Bit Implementations

In 32-bit implementations, the segment descriptors are 32-bits long and reside in one of 16

segment registers. Figure 27 shows the format of a segment register used in page address

translation (T = 0) in a 32-bit implementation.

Figure 27. Segment Register Format for Page Address Translation—32-Bit

Implementations

Table 22 provides the corresponding bit deﬁnitions of the segment register in 32-bit

implementations.

0 51 52 63

Physical Address of Segment Table 0 0 0 0 0 0 0 0 0 0 0 0

Reserved

01234 78 31

T Ks Kp N 0 0 0 0 VSID

Reserved

PowerPC Microprocessor Family: The Programmer’s Reference Guide 33

The Ks and Kp bits partially deﬁne the access protection for the pages within the segment.

The virtual segment ID ﬁeld is used as the high-order bits of the virtual page number

(VPN).

The segment register instructions are summarized in Table 23. These instructions are

privileged in that they are executable only while operating in supervisor mode.

2.2.3 Segment Descriptors for Direct-Store Segments

The format of many of the ﬁelds in the segment descriptors depends on the value of the

T bit. Figure 28 shows the format of segment descriptors (residing as STEs in segment

tables) that deﬁne direct-store segments for 64-bit implementations (T bit is set).

Table 22. Segment Register Bit Definition for Page Address Translation—32-Bit

Implementations

Bit Name Description

0 T T = 0 selects this format

Supervisor-state protection key

User-state protection key

3 N No-execute protection bit

4–7 — Reserved

8–31 VSID Virtual segment ID

Table 23. Segment Register Instructions—32-Bit Implementations Only

Instruction Description

mtsr SR,rS Move to Segment Register

SR[SR]← rS

mtsrin rS,rB Move to Segment Register Indirect

SR[rB[0–3]]←rS

mfsr rD,SR Move from Segment Register

rD←SR[SR]

mfsrin rD,rB Move from Segment Register Indirect

rD←SR[rB[0–3]]

34 PowerPC Microprocessor Family: The Programmer’s Reference Guide

Figure 28. Segment Descriptor Format for Direct-Store Segments—64-Bit

Implementations

Table 24 shows the bit deﬁnitions for the segment descriptors when the T bit is set for 64-

bit implementations.

In 32-bit implementations, the segment descriptors reside in one of 16 segment registers.

Figure 29 shows the register format for the segment registers when the T bit is set for 32-

bit implementations.

Figure 29. Segment Register Format for Direct-Store Segments—32-Bit

Implementations

Table 24. Segment Descriptor Bit Definitions for Direct-Store Segments—64-Bit

Implementations

Double Word Bit Name Description

0 0–35 ESID Effective segment ID

36–55 — Reserved

56 V Entry valid (V = 1) or invalid (V = 0)

57 T T = 0 selects this format

58 Ks Supervisor-state protection key

59 Kp User-state protection key

61–63 — Reserved

1 0–63 — Device speciﬁc data for I/O controller

Reserved

0 3536 555657585960 63

0 63

Controller-Specific Information

ESID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V T Ks Kp 0 0 0 0

Double Word 0

Double Word 1

T Ks Kp BUID Controller-Specific Information

0 1 2 3 11 12 31

PowerPC Microprocessor Family: The Programmer’s Reference Guide 35

Table 25 shows the bit deﬁnitions for the segment registers when the T bit is set for 32-bit

implementations.

2.3 Page Table Entry (PTE) Deﬁnitions

Page table entries (PTEs) are generated and placed in page tables in memory by the

operating system. The PowerPC OEA deﬁnes similar PTE formats for both 64- and 32-bit

implementations in that the same ﬁelds are deﬁned. However, 64-bit implementations

deﬁne PTEs that are 128 bits in length while 32-bit implementations deﬁne PTEs that are

64 bits in length. Additionally, care must be taken when programming for both 64 and 32-

bit implementations, as the bit placements of some ﬁelds are different. Some of the ﬁelds

are deﬁned as follows:

• The virtual segment ID field corresponds to the high-order bits of the virtual page

number (VPN), and, along with the H, V, and API fields, it is used to locate the PTE

(used as match criteria in comparing the PTE with the segment information).

• The R and C bits maintain history information for the page.

• The WIMG bits define the memory/cache control mode for accesses to the page.

• The PP bits deﬁne the remaining access protection constraints for the page.

Conceptually, the page table in memory must be searched to translate the address of every

reference.

2.3.1 PTE Format for 64-Bit Implementations

In 64-bit implementations, each PTE is a 128-bit entity (two double words) that maps a

virtual page number (VPN) to a physical page number (RPN). Information in the PTE is

used in the page table search process (to determine a page table hit) and provides input to

Table 25. Segment Register Bit Definitions for Direct-Store Segments

Bit Name Description

0 T T = 1 selects this format.

1 Ks Supervisor-state protection key

2 Kp User-state protection key

3–11 BUID Bus unit ID

12–31 — Device speciﬁc data for I/O controller

36 PowerPC Microprocessor Family: The Programmer’s Reference Guide

the memory protection mechanism. Figure 30 shows the format of the two double words

that comprise a PTE for 64-bit implementations.

Figure 30. Page Table Entry Format—64-Bit Implementations

Table 26 lists the corresponding bit deﬁnitions for each double word in a PTE as deﬁned

above.

The PTE contains an abbreviated page index rather than the complete page index ﬁeld

because at least 11 of the low-order bits of the page index are used in the hash function to

select a PTE group (PTEG) address (PTEG addresses deﬁne the location of a PTE).

Therefore, these 11 lower-order bits are not repeated in the PTEs of that PTEG.

Table 26. PTE Bit Definitions—64-Bit Implementations

Double

Word

Bit Name Description

0 0–51 VSID Virtual segment ID—corresponds to

the high-order bits of the virtual page

number (VPN)

52–56 API Abbreviated page index

57–61 — Reserved

62 H Hash function identiﬁer

63 V Entry valid (V = 1) or invalid (V = 0)

1 0–51 RPN Physical page number

52–54 — Reserved

55 R Referenced bit

56 C Changed bit

57–60 WIMG Memory/cache access control bits

61 — Reserved

62–63 PP Page protection bits

Reserved

051525455565760616263

051525657616263

RPN 0 0 0 R C WIMG 0 PP

VSID API 0 0 0 0 0 H V

PowerPC Microprocessor Family: The Programmer’s Reference Guide 37

2.3.2 PTE Format for 32-Bit Implementations

Figure 31 shows the format of the two words that comprise a PTE for 32-bit

implementations.

Figure 31. Page Table Entry Format—32-Bit Implementations

Table 27 lists the corresponding bit deﬁnitions for each word in a PTE as deﬁned above.

In this case, the PTE contains an abbreviated page index rather than the complete page

index ﬁeld because at least ten of the low-order bits of the page index are used in the hash

function to select a PTEG address (PTEG addresses deﬁne the location of a PTE).

Therefore, these ten lower-order bits are not repeated in the PTEs of that PTEG.

2.3.3 SDR1 Register Deﬁnitions

The SDR1 register contains the control information for the page table structure in that it

deﬁnes the highest order bits for the physical base address of the page table and it deﬁnes

the size of the table. The format of the SDR1 register differs for 64-bit and 32-bit

implementations, as shown below.

Table 27. PTE Bit Definitions—32-Bit Implementations

Word Bit Name Description

0 0 V Entry valid (V = 1) or invalid (V = 0)

1–24 VSID Virtual segment ID

25 H Hash function identiﬁer

26–31 API Abbreviated page index

1 0–19 RPN Physical page number

20–22 — Reserved

23 R Referenced bit

24 C Changed bit

25–28 WIMG Memory/cache control bits

29 — Reserved

30–31 PP Page protection bits

Reserved

0 1920 22232425 28293031

V VSID H API

01 24 25 26 31

RPN 0 0 0 R C WIMG 0 PP

38 PowerPC Microprocessor Family: The Programmer’s Reference Guide

2.3.3.1 SDR1 Register Deﬁnition for 64-Bit Implementations

The format of the SDR1 register for a 64-bit implementation is shown in Figure 32 and the

bit settings are described in Table 28.

Figure 32. SDR1 Register Format—64-Bit Implementations

The HTABORG ﬁeld in SDR1 contains the high-order 46 bits of the 64-bit physical address

of the page table. Therefore, the beginning of the page table lies on a 2

byte (256 Kbyte)

boundary at a minimum. If the processor does not support 64 bits of physical address,

software should write zeroes to those unsupported bits in the HTABORG ﬁeld (as the

implementation treats them as reserved). Otherwise, a machine check exception can occur.

A page table can be any size 2

bytes where 18 ≤ n ≤ 46. The HTABSIZE ﬁeld in SDR1

contains an integer value that speciﬁes how many bits from the output of the hashing

function are used as the page table index. HTABSIZE is used to generate a mask of the form

0b00...011...1 (a string of (HTABSIZE – 28) 0 bits followed by a string of 1 bits). As the

table size increases, more bits are used from the output of the hashing function to index into

the table. The 1 bits in the mask determine how many additional bits (beyond the minimum

of 11) from the hash are used in the index; the HTABORG ﬁeld must have this same

number of lower-order bits equal to 0.

2.3.3.2 SDR1 Register Deﬁnition for 32-Bit Implementations

The format of SDR1 for 32-bit implementations is similar to that of 64-bit implementations

except that the register size is 32 bits and the HTABMASK ﬁeld is programmed explicitly

into SDR1. Additionally, the address ranges correspond to a 32-bit physical address and the

range of page table sizes is smaller. Figure 33 shows the format of the SDR1 register for

32-bit implementations; the bit settings are described in Table 29.

Table 28. SDR1 Register Bit Settings—64-Bit Implementations

Bits Name Description

0–45 HTABORG Physical base address of page table

46–58 — Reserved

59-63 HTABSIZE Encoded size of page table (used to

generate mask)

0 0 0 0 0 0 0 0 0 0 0 0 0 HTABSIZE

Reserved

04546585963

HTABORG

PowerPC Microprocessor Family: The Programmer’s Reference Guide 39

Figure 33. SDR1 Register Format—32-Bit Implementations

The HTABORG ﬁeld in SDR1 contains the high-order 16 bits of the 32-bit physical address

of the page table. Therefore, the beginning of the page table lies on a 2

byte (64 Kbyte)

boundary at a minimum. As with 64-bit implementations, if the processor does not support

32 bits of physical address, software should write zeroes to those unsupported bits in the

HTABORG ﬁeld (as the implementation treats them as reserved). Otherwise, a machine

check exception can occur.

A page table can be any size 2

bytes where 16 ≤ n ≤ 25. The HTABMASK ﬁeld in SDR1

contains a mask value that determines how many bits from the output of the hashing

function are used as the page table index. This mask must be of the form 0b00...011...1 (a

string of 0 bits followed by a string of 1 bits). As the table size increases, more bits are used

from the output of the hashing function to index into the table. The 1 bits in HTABMASK

determine how many additional bits (beyond the minimum of 10) from the hash are used

in the index; the HTABORG ﬁeld must have the same number of lower-order bits equal to

0 as the HTABMASK ﬁeld has lower-order bits equal to 1.

Table 29. SDR1 Register Bit Settings—32-Bit Implementations

Bits Name Description

0–15 HTABORG Physical base address of page table

16–22 — Reserved

23–31 HTABMASK Mask for page table address

0 0 0 0 0 0 0 HTABMASK

Reserved

01516222331

HTABORG

40 PowerPC Microprocessor Family: The Programmer’s Reference Guide

Part 3 Exception Vectors

Exceptions, and conditions that cause them, are listed in Table 30.

Table 30. Exceptions and Conditions

Exception

Type

Vector Offset

(hex)

Causing Conditions

Reserved 00000 —

System reset 00100 The causes of system reset exceptions are implementation-dependent. If the

conditions that cause the exception also cause the processor state to be

corrupted such that the contents of SRR0 and SRR1 are no longer valid or such

that other processor resources are so corrupted that the processor cannot

reliably resume execution, the copy of the RI bit copied from the MSR to SRR1

is cleared.

Machine check 00200 The causes for machine check exceptions are implementation-dependent, but

typically these causes are related to conditions such as bus parity errors or

attempting to access an invalid physical address. Typically, these exceptions are

triggered by an input signal to the processor. Note that not all processors

provide the same level of error checking.

The machine check exception is disabled when MSR[ME] = 0. If a machine

check exception condition exists and the ME bit is cleared, the processor goes

into the checkstop state.

If the conditions that cause the exception also cause the processor state to be

corrupted such that the contents of SRR0 and SRR1 are no longer valid or such

that other processor resources are so corrupted that the processor cannot

reliably resume execution, the copy of the RI bit copied from the MSR to SRR1

is cleared.

DSI 00300 A DSI exception occurs when a data memory access cannot be performed.

Such accesses can be generated by load/store instructions, certain memory

control instructions, and certain cache control instructions. For more detailed

information, refer to Chapter 6, “Exceptions,” in

The Programming Environments

Manual

ISI 00400 An ISI exception occurs when an instruction fetch cannot be performed. For

more detailed information, refer to Chapter 6, “Exceptions,” in

The Programming

Environments Manual

External

interrupt

00500 An external interrupt is generated only when an external exception is pending

(typically signaled by a signal deﬁned by the implementation) and the interrupt is

enabled (MSR[EE] = 1).

Alignment 00600 An alignment exception may occur when the processor cannot perform a

memory access because of alignment or endian reasons.

Note that an implementation is allowed to perform the operation correctly and

not cause an alignment exception. For more detailed information, refer to

Chapter 6, “Exceptions,” in

The Programming Environments Manual

Program 00700 A program exception is caused conditions which correspond to bit settings in

SRR1 and arise during execution of an instruction. For more detailed

information, refer to Chapter 6, “Exceptions,” in

The Programming Environments

Manual

Floating-point

unavailable

00800 A ﬂoating-point unavailable exception is caused by an attempt to execute a

ﬂoating-point instruction (including ﬂoating-point load, store, and move

instructions) when the ﬂoating-point available bit is cleared, MSR[FP] = 0.

PowerPC Microprocessor Family: The Programmer’s Reference Guide 41

Part 4 PowerPC Instruction Set

The following sections include an instruction ﬁeld summary, a list of split-ﬁeld notation

and conventions, and the entire PowerPC instruction set, sorted by mnemonic and opcode.

4.1 Instruction Field Summary

Table 31 describes the instruction ﬁelds used in the various instruction formats.

Decrementer 00900 The decrementer interrupt exception is taken if the interrupt is enabled and the

exception is pending. The exception is created when the most signiﬁcant bit

changes from 0 to 1. If it is not enabled, the exception remains pending until it is

taken

Reserved 00A00 Reserved for implementation-speciﬁc exceptions. For example, the PowerPC

601 microprocessor uses this vector offset for direct-store exceptions.

Reserved 00B00 —

System call 00C00 A system call exception occurs when a System Call (sc) instruction is executed.

Trace 00D00 The trace exception is optional. It occurs if either the MSR[SE] = 1 and any

instruction (except rﬁ) successfully completed or MSR[BE] = 1 and a branch

instruction is completed.

Floating-Point

Assist

00E00 The ﬂoating-point assist exception is optional. This exception can be used to

provide software assistance for infrequent and complex ﬂoating-point operations

such as denormalization.

Reserved 00E10–00FFF —

Reserved 01000–02FFF Reserved for implementation-speciﬁc exceptions.

Table 31. Instruction Syntax Conventions

Field Description

AA (30) Absolute address bit.

0 The immediate ﬁeld represents an address relative to the current instruction address (CIA).

The effective (logical) address of the branch is either the sum of the LI ﬁeld sign-extended to

64 bits and the address of the branch instruction or the sum of the BD ﬁeld sign-extended to

64 bits and the address of the branch instruction.

1 The immediate ﬁeld represents an absolute address. The effective address (EA) of the branch

is the LI ﬁeld sign-extended to 64 bits or the BD ﬁeld sign-extended to 64 bits.

Note: The LI and BD ﬁelds are sign-extended to 32 bits in 32-bit implementations.

BD (16–29) Immediate ﬁeld specifying a 14-bit signed two's complement branch displacement that is

concatenated on the right with 0b00 and sign-extended to 64 bits (32 bits in 32-bit

implementations).

BI (11–15) Field used to specify a bit in the CR to be used as the condition of a branch conditional

instruction.

BO (6–10) Field used to specify options for the branch conditional instructions.

Table 30. Exceptions and Conditions (Continued)

Exception

Type

Vector Offset

(hex)

Causing Conditions

42 PowerPC Microprocessor Family: The Programmer’s Reference Guide

crbA (11–15) Field used to specify a bit in the CR to be used as a source.

crbB (16–20) Field used to specify a bit in the CR to be used as a source.

crbD (6–10) Field used to specify a bit in the CR, or in the FPSCR, as the destination of the result of an

instruction.

crfD (6–8) Field used to specify one of the CR ﬁelds, or one of the FPSCR ﬁelds, as a destination.

crfS (11–13) Field used to specify one of the CR ﬁelds, or one of the FPSCR ﬁelds, as a source.

CRM (12–19) Field mask used to identify the CR ﬁelds that are to be updated by the mtcrf instruction.

d (16–31) Immediate ﬁeld specifying a 16-bit signed two's complement integer that is sign-extended to 64

bits (32 bits in 32-bit implementations).

ds (16–29) Immediate ﬁeld specifying a 14-bit signed two’s complement integer which is concatenated on

the right with 0b00 and sign-extended to 64 bits. This ﬁeld is deﬁned in 64-bit implementations

only.

FM (7–14) Field mask used to identify the FPSCR ﬁelds that are to be updated by the mtfsf instruction.

frA (11–15) Field used to specify an FPR as a source.

frB (16–20) Field used to specify an FPR as a source.

frC (21–25) Field used to specify an FPR as a source.

frD (6–10) Field used to specify an FPR as the destination.

frS (6–10) Field used to specify an FPR as a source.

IMM (16–19) Immediate ﬁeld used as the data to be placed into a ﬁeld in the FPSCR.

L (10) Field used to specify whether an integer compare instruction is to compare 64-bit numbers or 32-

bit numbers. This ﬁeld is deﬁned in 64-bit implementations only.

LI (6–29) Immediate ﬁeld specifying a 24-bit signed two's complement integer that is concatenated on the

right with 0b00 and sign-extended to 64 bits (32 bits in 32-bit implementations).

LK (31) Link bit.

0 Does not update the link register (LR).

1 Updates the LR. If the instruction is a branch instruction, the address of the instruction

following the branch instruction is placed into the LR.

MB (21–25) and

ME (26–30)

Fields used in rotate instructions to specify a 64-bit mask (32 bits in 32-bit implementations)

consisting of 1 bits from bit MB + 32 through bit ME + 32 inclusive, and 0 bits elsewhere.

NB (16–20) Field used to specify the number of bytes to move in an immediate string load or store.

OE (21) Used for extended arithmetic to enable setting OV and SO in the XER.

OPCD (0–5) Primary opcode ﬁeld.

rA (11–15) Field used to specify a GPR to be used as a source or destination.

rB (16–20) Field used to specify a GPR to be used as a source.

Table 31. Instruction Syntax Conventions (Continued)

Field Description

PowerPC Microprocessor Family: The Programmer’s Reference Guide 43

Split ﬁelds—mb, me, sh, spr, and tbr—are described in Table 32.

Rc (31) Record bit.

0 Does not update the condition register (CR).

1 Updates the CR to reﬂect the result of the operation.

For integer instructions, CR bits 0–2 are set to reﬂect the result as a signed quantity and CR

bit 3 receives a copy of the summary overﬂow bit, XER[SO]. The result as an unsigned

quantity or a bit string can be deduced from the EQ bit. For ﬂoating-point instructions, CR bits

4–7 are set to reﬂect ﬂoating-point exception, ﬂoating-point enabled exception, ﬂoating-point

invalid operation exception, and ﬂoating-point overﬂow exception. (Note that the architecture

speciﬁcation refers to exceptions also as interrupts.)

rD (6–10) Field used to specify a GPR to be used as a destination.

rS (6–10) Field used to specify a GPR to be used as a source.

SH (16–20) Field used to specify a shift amount.

SIMM (16–31) Immediate ﬁeld used to specify a 16-bit signed integer.

SR (12–15) Field used to specify one of the 16 segment registers (32-bit implementations only).

TO (6–10) Field used to specify the conditions on which to trap.

UIMM (16–31) Immediate ﬁeld used to specify a 16-bit unsigned integer.

XO (21–29,

21–30, 22–30,

26–30, 27–29,

27–30, or 30–31)

Extended opcode ﬁeld.

Bits 21–29, 27–29, 27–30, 30–31 pertain to 64-bit implementations only.

Table 32. Split-Field Notation and Conventions

Field Description

mb (21–26) Field used in rotate instructions to specify the ﬁrst 1 bit of a 64-bit mask (32 bits in 32-bit

implementations). This ﬁeld is deﬁned in 64-bit implementations only.

me (21–26) Field used in rotate instructions to specify the last 1 bit of a 64-bit mask (32 bits in 32-bit

implementations). This ﬁeld is deﬁned in 64-bit implementations only.

sh (16–20) and

sh (30)

Fields used to specify a shift amount (64-bit implementations only).

spr (11–20) Field used to specify a special purpose register for the mtspr and mfspr instructions.

tbr (11–20) Field used to specify either the time base lower (TBL) or time base upper (TBU).

Table 31. Instruction Syntax Conventions (Continued)

Field Description

PowerPC Microprocessor Family: The Programmer’s Reference Guide

4.2 PowerPC Instruction Set Listings

This section lists the PowerPC architecture’s instruction set. Instructions are sorted by

mnemonic and opcode. Note

that split fields, that represent the concatenation of sequences

from left to right, are shown in lowercase.

Table 33 lists the instructions implemented in the PowerPC architecture in alphabetical

order by mnemonic.

Table 33. Complete Instruction List Sorted by Mnemonic

Name

0 678910111213141516171819202122232425262728293031

add

31 D A B OE 266 Rc

addc

31 D A B OE 10 Rc

adde

31 D A B OE 138 Rc

addi

14 D A SIMM

addic

12 D A SIMM

addic.

13 D A SIMM

addis

15 D A SIMM

addme

31 D A

0 0 0 0 0 OE 234 Rc

addze

31 D A

0 0 0 0 0 OE 202 Rc

and

31 S A B 28 Rc

andc

31 S A B 60 Rc

andi.

28 S A UIMM

andis.

29 S A UIMM

18 LI AA LK

16 BO BI BD AA LK

bcctr

19 BO BI

0 0 0 0 0 528 LK

bclr

19 BO BI

0 0 0 0 0 16 LK

cmp

31 crfD

0L A B 0 0

cmpi

11 crfD

0 L A SIMM

cmpl

31 crfD

0L A B 32 0

cmpli

10 crfD

0 L A UIMM

cntlzd

31 S A

0 0 0 0 0 58 Rc

cntlzw

31 S A

0 0 0 0 0 26 Rc

crand

19 crbD crbA crbB 257

Reserved bits

Key:

This document was created with FrameMaker 4.0.4

PowerPC Microprocessor Family: The Programmer’s Reference Guide

crandc

19 crbD crbA crbB 129

creqv

19 crbD crbA crbB 289

crnand

19 crbD crbA crbB 225

crnor

19 crbD crbA crbB 33

cror

19 crbD crbA crbB 449

crorc

19 crbD crbA crbB 417

crxor

19 crbD crbA crbB 193

dcbf

0 0 0 0 0 A B 86 0

dcbi

0 0 0 0 0 A B 470 0

dcbst

0 0 0 0 0 A B 54 0

dcbt

0 0 0 0 0 A B 278 0

dcbtst

0 0 0 0 0 A B 246 0

dcbz

0 0 0 0 0 A B 1014 0

divd

31 D A B OE 489 Rc

divdu

31 D A B OE 457 Rc

divw

31 D A B OE 491 Rc

divwu

31 D A B OE 459 Rc

eciwx

31 D A B 310

ecowx

31 S A B 438

eieio

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 854 0

eqv

31 S A B 284 Rc

extsb

31 S A

0 0 0 0 0 954 Rc

extsh

31 S A

0 0 0 0 0 922 Rc

extsw

31 S A 0 0 0 0 0 986 Rc

fabs

63 D

0 0 0 0 0 B 264 Rc

fadd

63 D A B

0 0 0 0 0 21 Rc

fadds

59 D A B

0 0 0 0 0 21 Rc

fcfid

63 D

0 0 0 0 0 B 846 Rc

fcmpo

63 crfD

0 0 A B 32 0

fcmpu

63 crfD

0 0 A B 0 0

fctid

63 D

0 0 0 0 0 B 814 Rc

fctidz

63 D

0 0 0 0 0 B 815 Rc

fctiw

63 D 0 0 0 0 0 B 14 Rc

Name

0 678910111213141516171819202122232425262728293031

PowerPC Microprocessor Family: The Programmer’s Reference Guide

fctiwz

63 D

0 0 0 0 0 B 15 Rc

fdiv

63 D A B

0 0 0 0 0 18 Rc

fdivs

59 D A B

0 0 0 0 0 18 Rc

fmadd

63 D A B C 29 Rc

fmadds

59 D A B C 29 Rc

fmr

63 D

0 0 0 0 0 B 72 Rc

fmsub

63 D A B C 28 Rc

fmsubs

59 D A B C 28 Rc

fmul

63 D A

0 0 0 0 0 C 25 Rc

fmuls

59 D A

0 0 0 0 0 C 25 Rc

fnabs

63 D

0 0 0 0 0 B 136 Rc

fneg

63 D

0 0 0 0 0 B 40 Rc

fnmadd

63 D A B C 31 Rc

fnmadds

59 D A B C 31 Rc

fnmsub

63 D A B C 30 Rc

fnmsubs

59 D A B C 30 Rc

fres

59 D

0 0 0 0 0 B 0 0 0 0 0 24 Rc

frsp

63 D

0 0 0 0 0 B 12 Rc

frsqrte

63 D

0 0 0 0 0 B 0 0 0 0 0 26 Rc

fsel

63 D A B C 23 Rc

fsqrt

63 D

0 0 0 0 0 B 0 0 0 0 0 22 Rc

fsqrts

59 D

0 0 0 0 0 B 0 0 0 0 0 22 Rc

fsub

63 D A B 0 0 0 0 0 20 Rc

fsubs

59 D A B

0 0 0 0 0 20 Rc

icbi

0 0 0 0 0 A B 982 0

isync

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 150 0

lbz

34 D A d

lbzu

35 D A d

lbzux

31 D A B 119

lbzx

31 D A B 87

58 D A ds 0

ldarx

31 D A B 84 0

ldu

58 D A ds 1

Name

0 678910111213141516171819202122232425262728293031

PowerPC Microprocessor Family: The Programmer’s Reference Guide

ldux

31 D A B 53

ldx

31 D A B 21

lfd

50 D A d

lfdu

51 D A d

lfdux

31 D A B 631

lfdx

31 D A B 599

lfs

48 D A d

lfsu

49 D A d

lfsux

31 D A B 567

lfsx

31 D A B 535

lha

42 D A d

lhau

43 D A d

lhaux

31 D A B 375

lhax

31 D A B 343

lhbrx

31 D A B 790

lhz

40 D A d

lhzu

41 D A d

lhzux

31 D A B 311

lhzx

31 D A B 279

lmw

46 D A d

lswi

31 D A NB 597

lswx

31 D A B 533

lwa

58 D A ds 2

lwarx

31 D A B 20 0

lwaux

31 D A B 373

lwax

31 D A B 341

lwbrx

31 D A B 534

lwz

32 D A d

lwzu

33 D A d

lwzux

31 D A B 55

lwzx

31 D A B 23

mcrf

19 crfD

0 0 crfS 0 0 0 0 0 0 0 0 0

mcrfs

63 crfD

0 0 crfS 0 0 0 0 0 0 0 64 0

Name

0 678910111213141516171819202122232425262728293031

PowerPC Microprocessor Family: The Programmer’s Reference Guide

mcrxr

31 crfD

0 0 0 0 0 0 0 0 0 0 0 0 512 0

mfcr 31 D

0 0 0 0 0 0 0 0 0 0 19 0

mffs

63 D 0 0 0 0 0 0 0 0 0 0 583 Rc

mfmsr

31 D 0 0 0 0 0 0 0 0 0 0 83 0

mfspr

31 D spr 339 0

mfsr

1,6

31 D 0

0 0 0 0 0 595 0

mfsrin

1,6

31 D 0 0 0 0 0 B 659 0

mftb 31 D tbr 371

mtcrf 31 S

CRM

0 144 0

mtfsb0

63 crbD 0 0 0 0 0 0 0 0 0 0 70 Rc

mtfsb1

63 crbD 0 0 0 0 0 0 0 0 0 0 38 Rc

mtfsf

63 0

0 B 711 Rc

mtfsfi

63 crfD 0 0 0 0 0 0 0

IMM

0 134 Rc

mtmsr

31 S 0 0 0 0 0 0 0 0 0 0 146 0

mtspr

31 S spr 467 0

mtsr

1,6

31 S 0

0 0 0 0 0 210 0

mtsrin

1,6

31 S 0 0 0 0 0 B 242 0

mulhd

31 D A B 073Rc

mulhdu

31 D A B 09Rc

mulhw

31 D A B 075Rc

mulhwu

31 D A B 011Rc

mulld

31 D A B OE 233 Rc

mulli 7 D A SIMM

mullw

31 D A B OE 235 Rc

nand

31 S A B 476 Rc

neg

31 D A 0 0 0 0 0 OE 104 Rc

nor

31 S A B 124 Rc

31 S A B 444 Rc

orc

31 S A B 412 Rc

ori 24 S A UIMM

oris 25 S A UIMM

rfi

19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0

rldcl

30 S A B mb 8 Rc

Name

0 678910111213141516171819202122232425262728293031

PowerPC Microprocessor Family: The Programmer’s Reference Guide 49

rldcr

30 S A B me 9 Rc

rldic

30 S A sh mb 2

rldicl

30 S A sh mb 0

rldicr

30 S A sh me 1

rldimi

30 S A sh mb 3

rlwimi

20 S A SH MB ME Rc

rlwinm

21 S A SH MB ME Rc

rlwnm

23 S A B MB ME Rc

sc 17

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

slbia

1,4,5

31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 498 0

slbie

1,4,5

31 0 0 0 0 0 0 0 0 0 0 B 434 0

sld

31 S A B 27 Rc

slw

31 S A B 24 Rc

srad

31 S A B 794 Rc

sradi

31 S A sh 413

sraw

31 S A B 792 Rc

srawi

31 S A SH 824 Rc

srd

31 S A B 539 Rc

srw

31 S A B 536 Rc

stb 38 S A d

stbu 39 S A d

stbux 31 S A B 247

stbx 31 S A B 215

std

62 S A ds 0

stdcx.

31 S A B 214 1

stdu

62 S A ds 1

stdux

31 S A B 181 0

stdx

31 S A B 149 0

stfd 54 S A d

stfdu 55 S A d

stfdux 31 S A B 759

stfdx 31 S A B 727

stfiwx

31 S A B 983 0

Name

0 678910111213141516171819202122232425262728293031

50 PowerPC Microprocessor Family: The Programmer’s Reference Guide

stfs 52 S A d

stfsu 53 S A d

stfsux 31 S A B 695

stfsx 31 S A B 663

sth 44 S A d

sthbrx 31 S A B 918

sthu 45 S A d

sthux 31 S A B 439

sthx 31 S A B 407

stmw

47 S A d

stswi

31 S A NB 725 0

stswx

31 S A B 661 0

stw 36 S A d

stwbrx 31 S A B 662

stwcx. 31 S A B 150 1

stwu 37 S A d

stwux 31 S A B 183

stwx 31 S A B 151

subf

31 D A B OE 40 Rc

subfc

31 D A B OE 8 Rc

subfe

31 D A B OE 136 Rc

subfic 08 D A SIMM

subfme

31 D A 0 0 0 0 0 OE 232 Rc

subfze

31 D A 0 0 0 0 0 OE 200 Rc

sync 31

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 598 0

31 TO A B 68 0

tdi

02 TO A SIMM

tlbia

1,5

31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 370 0

tlbie

1,5

31 0 0 0 0 0 0 0 0 0 0 B 306 0

tlbsync

1,5

31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 566 0

tw 31 TO A B 4

twi 03 TO A SIMM

xor

31 S A B 316 Rc

Name

0 678910111213141516171819202122232425262728293031

PowerPC Microprocessor Family: The Programmer’s Reference Guide 51

Table 34 lists the instructions deﬁned in the PowerPC architecture in numeric order by

opcode.

Table 34. Complete Instruction List Sorted by Opcode

xori 26 S A UIMM

xoris 27 S A UIMM

Supervisor-level instruction

Supervisor- and user-level instruction

Load and store string or multiple instruction

64-bit instruction

Optional instruction

32-bit instruction only

Name

0 5678910111213141516171819202122232425262728293031

tdi

0 0 0 0 1 0 TO A SIMM

twi 0 0 0 0 1 1 TO A SIMM

mulli 0 0 0 1 1 1 D A SIMM

subfic 0 0 1 0 0 0 D A SIMM

cmpli 0 0 1 0 1 0 crfD

0 L A UIMM

cmpi 0 0 1 0 1 1 crfD

0 L A SIMM

addic 0 0 1 1 0 0 D A SIMM

addic. 0 0 1 1 0 1 D A SIMM

addi 0 0 1 1 1 0 D A SIMM

addis 0 0 1 1 1 1 D A SIMM

0 1 0 0 0 0 BO BI BD AA LK

sc 0 1 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

0 1 0 0 1 0 LI AA LK

mcrf 0 1 0 0 1 1 crfD

0 0 crfS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

bclr

0 1 0 0 1 1 BO BI 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 LK

crnor 0 1 0 0 1 1 crbD crbA crbB 0 0 0 0 1 0 0 0 0 1

rfi 0 1 0 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0

crandc 0 1 0 0 1 1 crbD crbA crbB 0 0 1 0 0 0 0 0 0 1

isync 0 1 0 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0

crxor 0 1 0 0 1 1 crbD crbA crbB 0 0 1 1 0 0 0 0 0 1

Name

0 678910111213141516171819202122232425262728293031

Reserved bits

Key:

52 PowerPC Microprocessor Family: The Programmer’s Reference Guide

crnand 0 1 0 0 1 1 crbD crbA crbB 0 0 1 1 1 0 0 0 0 1 0

crand 0 1 0 0 1 1 crbD crbA crbB 0 1 0 0 0 0 0 0 0 1

creqv 0 1 0 0 1 1 crbD crbA crbB 0 1 0 0 1 0 0 0 0 1

crorc 0 1 0 0 1 1 crbD crbA crbB 0 1 1 0 1 0 0 0 0 1

cror 0 1 0 0 1 1 crbD crbA crbB 0 1 1 1 0 0 0 0 0 1

bcctr

0 1 0 0 1 1 BO BI 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 LK

rlwimi

0 1 0 1 0 0 S A SH MB ME Rc

rlwinm

0 1 0 1 0 1 S A SH MB ME Rc

rlwnm

0 1 0 1 1 1 S A B MB ME Rc

ori 0 1 1 0 0 0 S A UIMM

oris 0 1 1 0 0 1 S A UIMM

xori 0 1 1 0 1 0 S A UIMM

xoris 0 1 1 0 1 1 S A UIMM

andi. 0 1 1 1 0 0 S A UIMM

andis. 0 1 1 1 0 1 S A UIMM

rldicl

0 1 1 1 1 0 S A sh mb 0 0 0

rldicr

0 1 1 1 1 0 S A sh me 0 0 1

rldic

0 1 1 1 1 0 S A sh mb 0 1 0

rldimi

0 1 1 1 1 0 S A sh mb 0 1 1

rldcl

0 1 1 1 1 0 S A B mb 0 1 0 0 0 Rc

rldcr

0 1 1 1 1 0 S A B me 0 1 0 0 1 Rc

cmp 0 1 1 1 1 1 crfD

0 L A B 0 0 0 0 0 0 0 0 0 0 0

tw 0 1 1 1 1 1 TO A B 0 0 0 0 0 0 0 1 0 0

subfc

0 1 1 1 1 1 D A B OE 0 0 0 0 0 0 1 0 0 0 Rc

mulhdu

0 1 1 1 1 1 D A B 0 0 0 0 0 0 0 1 0 0 1 Rc

addc

0 1 1 1 1 1 D A B OE 0 0 0 0 0 0 1 0 1 0 Rc

mulhwu

0 1 1 1 1 1 D A B 0 0 0 0 0 0 0 1 0 1 1 Rc

mfcr 0 1 1 1 1 1 D

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0

lwarx 0 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 0 0

ldx

0 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 0 1 0

lwzx 0 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 1 1

slw

0 1 1 1 1 1 S A B 0 0 0 0 0 1 1 0 0 0 Rc

cntlzw

0 1 1 1 1 1 S A 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 Rc

Name

0 5678910111213141516171819202122232425262728293031

PowerPC Microprocessor Family: The Programmer’s Reference Guide 53

sld

0 1 1 1 1 1 S A B 0 0 0 0 0 1 1 0 1 1 Rc

and

0 1 1 1 1 1 S A B 0 0 0 0 0 1 1 1 0 0 Rc

cmpl 0 1 1 1 1 1 crfD

0 L A B 0 0 0 0 1 0 0 0 0 0 0

subf

0 1 1 1 1 1 D A B OE 0 0 0 0 1 0 1 0 0 0 Rc

ldux

0 1 1 1 1 1 D A B 0 0 0 0 1 1 0 1 0 1 0

dcbst 0 1 1 1 1 1

0 0 0 0 0 A B 0 0 0 0 1 1 0 1 1 0 0

lwzux 0 1 1 1 1 1 D A B 0 0 0 0 1 1 0 1 1 1

cntlzd

0 1 1 1 1 1 S A 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 Rc

andc

0 1 1 1 1 1 S A B 0 0 0 0 1 1 1 1 0 0 Rc

0 1 1 1 1 1 TO A B 0 0 0 1 0 0 0 1 0 0 0

mulhd

0 1 1 1 1 1 D A B 0 0 0 0 1 0 0 1 0 0 1 Rc

mulhw

0 1 1 1 1 1 D A B 0 0 0 0 1 0 0 1 0 1 1 Rc

mfmsr 0 1 1 1 1 1 D

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0

ldarx

0 1 1 1 1 1 D A B 0 0 0 1 0 1 0 1 0 0 0

dcbf 0 1 1 1 1 1

0 0 0 0 0 A B 0 0 0 1 0 1 0 1 1 0 0

lbzx 0 1 1 1 1 1 D A B 0 0 0 1 0 1 0 1 1 1

neg

0 1 1 1 1 1 D A 0 0 0 0 0 OE 0 0 0 1 1 0 1 0 0 0 Rc

lbzux 0 1 1 1 1 1 D A B 0 0 0 1 1 1 0 1 1 1

nor

0 1 1 1 1 1 S A B 0 0 0 1 1 1 1 1 0 0 Rc

subfe

0 1 1 1 1 1 D A B OE 0 0 1 0 0 0 1 0 0 0 Rc

adde

0 1 1 1 1 1 D A B OE 0 0 1 0 0 0 1 0 1 0 Rc

mtcrf 0 1 1 1 1 1 S

CRM

0 0 0 1 0 0 1 0 0 0 0 0

mtmsr 0 1 1 1 1 1 S

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0

stdx

0 1 1 1 1 1 S A B 0 0 1 0 0 1 0 1 0 1 0

stwcx. 0 1 1 1 1 1 S A B 0 0 1 0 0 1 0 1 1 0 1

stwx 0 1 1 1 1 1 S A B 0 0 1 0 0 1 0 1 1 1

stdux

0 1 1 1 1 1 S A B 0 0 1 0 1 1 0 1 0 1 0

stwux 0 1 1 1 1 1 S A B 0 0 1 0 1 1 0 1 1 1

subfze

0 1 1 1 1 1 D A 0 0 0 0 0 OE 0 0 1 1 0 0 1 0 0 0 Rc

addze

0 1 1 1 1 1 D A 0 0 0 0 0 OE 0 0 1 1 0 0 1 0 1 0 Rc

mtsr

1,6

0 1 1 1 1 1 S 0

0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0

stdcx.

0 1 1 1 1 1 S A B 0 0 1 1 0 1 0 1 1 0 1

stbx 0 1 1 1 1 1 S A B 0 0 1 1 0 1 0 1 1 1

Name

0 5678910111213141516171819202122232425262728293031

54 PowerPC Microprocessor Family: The Programmer’s Reference Guide

subfme

0 1 1 1 1 1 D A 0 0 0 0 0 OE 0 0 1 1 1 0 1 0 0 0 Rc

mulld

0 1 1 1 1 1 D A B OE 0 0 1 1 1 0 1 0 0 1 Rc

addme

0 1 1 1 1 1 D A 0 0 0 0 0 OE 0 0 1 1 1 0 1 0 1 0 Rc

mullw

0 1 1 1 1 1 D A B OE 0 0 1 1 1 0 1 0 1 1 Rc

mtsrin

1,6

0 1 1 1 1 1 S 0 0 0 0 0 B 0 0 1 1 1 1 0 0 1 0 0

dcbtst 0 1 1 1 1 1

0 0 0 0 0 A B 0 0 1 1 1 1 0 1 1 0 0

stbux 0 1 1 1 1 1 S A B 0 0 1 1 1 1 0 1 1 1

add

0 1 1 1 1 1 D A B OE 0 1 0 0 0 0 1 0 1 0 Rc

dcbt 0 1 1 1 1 1

0 0 0 0 0 A B 0 1 0 0 0 1 0 1 1 0 0

lhzx 0 1 1 1 1 1 D A B 0 1 0 0 0 1 0 1 1 1

eqv

0 1 1 1 1 1 S A B 0 1 0 0 0 1 1 1 0 0 Rc

tlbie

1,5

0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 B 0 1 0 0 1 1 0 0 1 0 0

eciwx 0 1 1 1 1 1 D A B 0 1 0 0 1 1 0 1 1 0

lhzux 0 1 1 1 1 1 D A B 0 1 0 0 1 1 0 1 1 1

xor

0 1 1 1 1 1 S A B 0 1 0 0 1 1 1 1 0 0 Rc

mfspr

0 1 1 1 1 1 D spr 0 1 0 1 0 1 0 0 1 1 0

lwax

0 1 1 1 1 1 D A B 0 1 0 1 0 1 0 1 0 1 0

lhax 0 1 1 1 1 1 D A B 0 1 0 1 0 1 0 1 1 1

tlbia

1,5

0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0

mftb 0 1 1 1 1 1 D tbr 0 1 0 1 1 1 0 0 1 1

lwaux

0 1 1 1 1 1 D A B 0 1 0 1 1 1 0 1 0 1 0

lhaux 0 1 1 1 1 1 D A B 0 1 0 1 1 1 0 1 1 1

sthx 0 1 1 1 1 1 S A B 0 1 1 0 0 1 0 1 1 1

orc

0 1 1 1 1 1 S A B 0 1 1 0 0 1 1 1 0 0 Rc

sradi

0 1 1 1 1 1 S A sh 1 1 0 0 1 1 1 0 1 1

slbie

1,4,5

0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 B 0 1 1 0 1 1 0 0 1 0 0

ecowx 0 1 1 1 1 1 S A B 0 1 1 0 1 1 0 1 1 0

sthux 0 1 1 1 1 1 S A B 0 1 1 0 1 1 0 1 1 1

0 1 1 1 1 1 S A B 0 1 1 0 1 1 1 1 0 0 Rc

divdu

0 1 1 1 1 1 D A B OE 0 1 1 1 0 0 1 0 0 1 Rc

divwu

0 1 1 1 1 1 D A B OE 0 1 1 1 0 0 1 0 1 1 Rc

mtspr

0 1 1 1 1 1 S spr 0 1 1 1 0 1 0 0 1 1 0

dcbi 0 1 1 1 1 1

0 0 0 0 0 A B 0 1 1 1 0 1 0 1 1 0 0

Name

0 5678910111213141516171819202122232425262728293031

PowerPC Microprocessor Family: The Programmer’s Reference Guide 55

nand

0 1 1 1 1 1 S A B 0 1 1 1 0 1 1 1 0 0 Rc

divd

0 1 1 1 1 1 D A B OE 0 1 1 1 1 0 1 0 0 1 Rc

divw

0 1 1 1 1 1 D A B OE 0 1 1 1 1 0 1 0 1 1 Rc

slbia

1,4,5

0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0

mcrxr 0 1 1 1 1 1 crfD

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

lswx

0 1 1 1 1 1 D A B 1 0 0 0 0 1 0 1 0 1 0

lwbrx 0 1 1 1 1 1 D A B 1 0 0 0 0 1 0 1 1 0

lfsx 0 1 1 1 1 1 D A B 1 0 0 0 0 1 0 1 1 1

srw

0 1 1 1 1 1 S A B 1 0 0 0 0 1 1 0 0 0 Rc

srd

0 1 1 1 1 1 S A B 1 0 0 0 0 1 1 0 1 1 Rc

tlbsync

1,5

0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0

lfsux 0 1 1 1 1 1 D A B 1 0 0 0 1 1 0 1 1 1

mfsr

1,6

0 1 1 1 1 1 D 0

0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0

lswi

0 1 1 1 1 1 D A NB 1 0 0 1 0 1 0 1 0 1 0

sync 0 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 0

lfdx 0 1 1 1 1 1 D A B 1 0 0 1 0 1 0 1 1 1

lfdux 0 1 1 1 1 1 D A B 1 0 0 1 1 1 0 1 1 1

mfsrin

1,6

0 1 1 1 1 1 D 0 0 0 0 0 B 1 0 1 0 0 1 0 0 1 1 0

stswx

0 1 1 1 1 1 S A B 1 0 1 0 0 1 0 1 0 1 0

stwbrx 0 1 1 1 1 1 S A B 1 0 1 0 0 1 0 1 1 0

stfsx 0 1 1 1 1 1 S A B 1 0 1 0 0 1 0 1 1 1

stfsux 0 1 1 1 1 1 S A B 1 0 1 0 1 1 0 1 1 1

stswi

0 1 1 1 1 1 S A NB 1 0 1 1 0 1 0 1 0 1 0

stfdx 0 1 1 1 1 1 S A B 1 0 1 1 0 1 0 1 1 1

stfdux 0 1 1 1 1 1 S A B 1 0 1 1 1 1 0 1 1 1

lhbrx 0 1 1 1 1 1 D A B 1 1 0 0 0 1 0 1 1 0

sraw

0 1 1 1 1 1 S A B 1 1 0 0 0 1 1 0 0 0 Rc

srad

0 1 1 1 1 1 S A B 1 1 0 0 0 1 1 0 1 0 Rc

srawi

0 1 1 1 1 1 S A SH 1 1 0 0 1 1 1 0 0 0 Rc

eieio 0 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0

sthbrx 0 1 1 1 1 1 S A B 1 1 1 0 0 1 0 1 1 0

extsh

0 1 1 1 1 1 S A 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 Rc

extsb

0 1 1 1 1 1 S A 0 0 0 0 0 1 1 1 0 1 1 1 0 1 0 Rc

Name

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56 PowerPC Microprocessor Family: The Programmer’s Reference Guide

icbi 0 1 1 1 1 1 0 0 0 0 0 A B 1 1 1 1 0 1 0 1 1 0 0

stfiwx

0 1 1 1 1 1 S A B 1 1 1 1 0 1 0 1 1 1 0

extsw

0 1 1 1 1 1 S A 0 0 0 0 0 1 1 1 1 0 1 1 0 1 0 Rc

dcbz 0 1 1 1 1 1

0 0 0 0 0 A B 1 1 1 1 1 1 0 1 1 0 0

lwz 1 0 0 0 0 0 D A d

lwzu 1 0 0 0 0 1 D A d

lbz 1 0 0 0 1 0 D A d

lbzu 1 0 0 0 1 1 D A d

stw 1 0 0 1 0 0 S A d

stwu 1 0 0 1 0 1 S A d

stb 1 0 0 1 1 0 S A d

stbu 1 0 0 1 1 1 S A d

lhz 1 0 1 0 0 0 D A d

lhzu 1 0 1 0 0 1 D A d

lha 1 0 1 0 1 0 D A d

lhau 1 0 1 0 1 1 D A d

sth 1 0 1 1 0 0 S A d

sthu 1 0 1 1 0 1 S A d

lmw

1 0 1 1 1 0 D A d

stmw

1 0 1 1 1 1 S A d

lfs 1 1 0 0 0 0 D A d

lfsu 1 1 0 0 0 1 D A d

lfd 1 1 0 0 1 0 D A d

lfdu 1 1 0 0 1 1 D A d

stfs 1 1 0 1 0 0 S A d

stfsu 1 1 0 1 0 1 S A d

stfd 1 1 0 1 1 0 S A d

stfdu 1 1 0 1 1 1 S A d

1 1 1 0 1 0 D A ds 0 0

ldu

1 1 1 0 1 0 D A ds 0 1

lwa

1 1 1 0 1 0 D A ds 1 0

fdivs

1 1 1 0 1 1 D A B 0 0 0 0 0 1 0 0 1 0 Rc

fsubs

1 1 1 0 1 1 D A B 0 0 0 0 0 1 0 1 0 0 Rc

Name

0 5678910111213141516171819202122232425262728293031

PowerPC Microprocessor Family: The Programmer’s Reference Guide 57

fadds

1 1 1 0 1 1 D A B 0 0 0 0 0 1 0 1 0 1 Rc

fsqrts

1 1 1 0 1 1 D 0 0 0 0 0 B 0 0 0 0 0 1 0 1 1 0 Rc

fres

1 1 1 0 1 1 D 0 0 0 0 0 B 0 0 0 0 0 1 1 0 0 0 Rc

fmuls

1 1 1 0 1 1 D A 0 0 0 0 0 C 1 1 0 0 1 Rc

fmsubs

1 1 1 0 1 1 D A B C 1 1 1 0 0 Rc

fmadds

1 1 1 0 1 1 D A B C 1 1 1 0 1 Rc

fnmsubs

1 1 1 0 1 1 D A B C 1 1 1 1 0 Rc

fnmadds

1 1 1 0 1 1 D A B C 1 1 1 1 1 Rc

std

1 1 1 1 1 0 S A ds 0 0

stdu

1 1 1 1 1 0 S A ds 0 1

fcmpu 1 1 1 1 1 1 crfD

0 0 A B 0 0 0 0 0 0 0 0 0 0 0

frsp

1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 0 0 0 1 1 0 0 Rc

fctiw

1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 0 0 0 1 1 1 0

fctiwz

1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 0 0 0 1 1 1 1 Rc

fdiv

1 1 1 1 1 1 D A B 0 0 0 0 0 1 0 0 1 0 Rc

fsub

1 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 0 0 Rc

fadd

1 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 0 1 Rc

fsqrt

1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 0 0 1 0 1 1 0 Rc

fsel

1 1 1 1 1 1 D A B C 1 0 1 1 1 Rc

fmul

1 1 1 1 1 1 D A 0 0 0 0 0 C 1 1 0 0 1 Rc

frsqrte

1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 0 0 1 1 0 1 0 Rc

fmsub

1 1 1 1 1 1 D A B C 1 1 1 0 0 Rc

fmadd

1 1 1 1 1 1 D A B C 1 1 1 0 1 Rc

fnmsub

1 1 1 1 1 1 D A B C 1 1 1 1 0 Rc

fnmadd

1 1 1 1 1 1 D A B C 1 1 1 1 1 Rc

fcmpo 1 1 1 1 1 1 crfD

0 0 A B 0 0 0 0 1 0 0 0 0 0 0

mtfsb1

1 1 1 1 1 1 crbD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 Rc

fneg

1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 0 1 0 1 0 0 0 Rc

mcrfs 1 1 1 1 1 1 crfD

0 0 crfS 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

mtfsb0

1 1 1 1 1 1 crbD 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 Rc

fmr

1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 1 0 0 1 0 0 0 Rc

mtfsfi

1 1 1 1 1 1 crfD 0 0 0 0 0 0 0

IMM

0 0 0 1 0 0 0 0 1 1 0 Rc

fnabs

1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 1 0 0 0 1 0 0 0 Rc

Name

0 5678910111213141516171819202122232425262728293031

58 PowerPC Microprocessor Family: The Programmer’s Reference Guide

fabs

1 1 1 1 1 1 D 0 0 0 0 0 B 0 1 0 0 0 0 1 0 0 0 Rc

mffs

1 1 1 1 1 1 D 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 Rc

mtfsf

1 1 1 1 1 1 0

0 B 1 0 1 1 0 0 0 1 1 1 Rc

fctid

1 1 1 1 1 1 D 0 0 0 0 0 B 1 1 0 0 1 0 1 1 1 0 Rc

fctidz

1 1 1 1 1 1 D 0 0 0 0 0 B 1 1 0 0 1 0 1 1 1 1 Rc

fcfid

1 1 1 1 1 1 D 0 0 0 0 0 B 1 1 0 1 0 0 1 1 1 0 Rc

Supervisor-level instruction

Supervisor- and user-level instruction

Load and store string or multiple instruction

64-bit instruction

Optional instruction

32-bit instruction only

Name

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